Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

Abstract: A cover for an electrical connector includes substrate mounting beams. When a force is applied to the top, the beams transfer the force to the lead frame, pressing contacts of the connector to an electrical device such as a substrate. Flat rock application may be applied to the top of the cover to connect the connector to a substrate. The cover may aid in retaining the lead frame assemblies in the connector. A cover for an electrical connector may include a back extending from a top such that the back includes resiliency and is able to be flexed while the cover is placed on a connector and flexed to remove the cover from the connector.

Abstract: A connector system includes a first connector, and a second connector that mates with the first connector. The same type of power contact is used in the first and second connectors.

Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

Abstract: A contact detector having power switches for disconnecting power to portions of the contact sensor when an over current is detected is disclosed. The power switches thus protect the contact sensor from over-current as the result of latch-up or other current-generating conditions. These current-generating conditions are often the result of ESD events on a surface of the contact detector. A contact detector comprises an exposed surface for detecting the presence of an object, an insulating surface, and a protection element disposed under the insulating surface for controlling power to the contact detector. The protection element is configured to disconnect power to the contact detector when a current to the contact detector is detected above a threshold. Preferably, the contact detector is a finger swipe sensor, but it can be a finger placement sensor or any other type of device that functions on contact with a finger or other patterned object.

Abstract: A cover for an electrical connector includes substrate mounting beams. When a force is applied to the top, the beams transfer the force to the lead frame, pressing contacts of the connector to an electrical device such as a substrate. Flat rock application may be applied to the top of the cover to connect the connector to a substrate. The cover may aid in retaining the lead frame assemblies in the connector. A cover for an electrical connector may include a back extending from a top such that the back includes resiliency and is able to be flexed while the cover is placed on a connector and flexed to remove the cover from the connector.

Abstract: Preferred embodiments of power contacts have alignment features that can maintain conductors of the power contacts in a state of alignment during and after insertion of the power contacts into a housing.

Abstract: Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.

Abstract: A first contact beam of a receptacle contact may define an indentation and a second contact beam may define a protrusion such that the protrusion may at least partially extend into the indentation. The protrusion may extend across the center of the receptacle contacts, and therefore the normal force created by each contact beam may be exerted against the normal force created by the other contact beam. Thus, rotation of a blade contact inserted into the receptacle contact may be reduced or eliminated. The contact beams of the receptacle contact may each include a formed area placed at different locations on the receptacle contact. A blade contact may overcome the normal force and mechanical resistance of a formed area of one of the contact beams before being confronted by the normal force and mechanical resistance of the other beam's formed area.

Abstract: A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract: An electrical connector may include a connector housing and a terminal tray. The terminal tray may include a tray body having a latch extending therefrom. The connector housing may define a latch receiving window. The latch and latch receiving window may be disposed such that the latch engages the latch receiving window only when the terminal tray is received in the housing in a preferred orientation. The terminal tray may include an electrically conductive contact having a board receiving end adapted to receive a printed circuit board and to exert sufficient pressure on the printed circuit board to retain the printed circuit board between the contact and the tray body. The connector may also include a plurality of cables bundled by a band, such as double-sided tape, such that respective portions of the cables are restrained from movement relative to one another.

Abstract: The system and method of the present invention is directed to emulating and configuring any of a plurality of electronic input devices. A system in accordance with one embodiment of the present invention comprises an interface and an emulator. The interface is for selecting and configuring an electronic input device from a plurality of electronic input devices, and the emulator is for emulating the electronic input device. Preferably, the plurality of electronic input devices comprise any two or more of a scroll wheel, a mouse, a joy stick, a steering wheel, an analog button, and a touch bar. Also in a preferred embodiment, the interface is an Application Programming Interface (API) and the emulator comprises a finger swipe sensor for receiving user input.

Abstract: A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

Abstract: A ring oscillator is formed using inverting stages configured from asymmetrical dual gated FET (ADG-FET) devices. The simplest form uses an odd number of CMOS inverter stages configured with an ADG-PFET and an ADG-NFET. The front gates are used as the logic inputs and are coupled to preceeding outputs from the main ring. The back gates of the ADG-PFET devices are coupled to a first control voltage and the back gates of the ADG-NFET devices are coupled to a second control voltage that is the complement of the first control voltage referenced to an off-set voltage. Other configurations of logic inverting stages using ADG-FET devices may also be used. The control voltage is varied to modulate the current level set by the logic state at the inputs coupled to the front gates.

Abstract: Preferred embodiments of power contacts include two or more opposing contact beams of a first type that are spaced apart along at least a portion of the length thereof when the power contact is in an unmated state; and two or more opposing contact beams of a second type. The contact beams of the second type are spaced apart so that the contact beams of the second type pinch the contact beams of the first type when the power contact is mated with a mating contact, thereby causing the contact beams of the first type of deflect inwardly toward each other.

Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.