Patents by Inventor Hung Q. Nguyen
Hung Q. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8788987Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: April 6, 2011Date of Patent: July 22, 2014Assignee: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8674749Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: GrantFiled: March 17, 2010Date of Patent: March 18, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu AAron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Patent number: 8650514Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: March 21, 2012Date of Patent: February 11, 2014Assignee: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Publication number: 20140037635Abstract: Novel IL-17 like polypeptides and nucleic acid molecules encoding the same. The invention also provides vectors, host cells, selective binding agents, and methods for producing IL-17 like polypeptides. Also provided for are methods for the treatment, diagnosis, amelioration, or prevention of diseases with IL-17 like polypeptides, agonists, or antagonists thereof.Type: ApplicationFiled: June 26, 2013Publication date: February 6, 2014Applicant: Amgen Inc.Inventors: Eugene MEDLOCK, Gary S. ELLIOTT, Shuqian JING, Scott Michael SILBIGER, Hung Q. NGUYEN, Richard YEH
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Patent number: 8497667Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: GrantFiled: November 29, 2011Date of Patent: July 30, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Patent number: 8456904Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: June 29, 2011Date of Patent: June 4, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Publication number: 20130097575Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: ApplicationFiled: April 6, 2011Publication date: April 18, 2013Applicant: TABULA, INC.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8300494Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: December 28, 2010Date of Patent: October 30, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Publication number: 20120231006Abstract: Disclosed is an isolated antigen binding proteins, such as but not limited to, an antibody or antibody fragment, that specifically bind to SEQ ID NO: 4, the amino acid sequence of extracellular loop 2 (ECL2) of human Orai1. Also disclosed are pharmaceutical compositions and medicaments comprising the antigen binding protein, isolated nucleic acid encoding it, vectors and host cells useful in methods of making it, and methods of using it in treating disorders or diseases in patients.Type: ApplicationFiled: November 19, 2010Publication date: September 13, 2012Applicant: Amgen Inc.Inventors: Hung Q. Nguyen, Fen-Fen Lin, Xiao-juan Bi, Helen J. McBride, Shaw-Fen Sylvia Hu
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Publication number: 20120176155Abstract: A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a resealed set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the resealed set of circuits.Type: ApplicationFiled: March 21, 2012Publication date: July 12, 2012Applicant: TABULA, INC.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8138524Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.Type: GrantFiled: November 1, 2006Date of Patent: March 20, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Alexander Kotov, Amitay Levi, Hung Q. Nguyen, Pavel Klinger
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Patent number: 8072815Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: December 10, 2010Date of Patent: December 6, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 8067931Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: GrantFiled: January 10, 2011Date of Patent: November 29, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang
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Patent number: 8043829Abstract: Disclosed is a composition of matter comprising a ShK toxin peptide analog, and in some embodiments, a pharmaceutically acceptable salt thereof. A pharmaceutical composition comprises the composition and a pharmaceutically acceptable carrier. Also disclosed are DNAs encoding the inventive composition of matter, an expression vector comprising the DNA, and host cells comprising the expression vector. Methods of treating an autoimmune disorder and of preventing or mitigating a relapse of a symptom of multiple sclerosis are also disclosed.Type: GrantFiled: October 25, 2007Date of Patent: October 25, 2011Assignee: Amgen Inc.Inventors: John K. Sullivan, Joseph G. McGivern, Leslie P. Miranda, Hung Q. Nguyen, Kenneth W. Walker, Shaw-Fen Sylvia Hu, Colin V. Gegg, Jr., Taruna Arora Khare, Beverly S. Adler, Francis H. Martin
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Publication number: 20110255346Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Microchip Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Patent number: 8018773Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: March 4, 2009Date of Patent: September 13, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 7990773Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.Type: GrantFiled: November 20, 2009Date of Patent: August 2, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
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Publication number: 20110160438Abstract: The present invention provides for IL-17 receptor like polypeptides and nucleic acid molecules encoding the same. The invention also provides vectors, host cells, agonists and antagonists (including selective binding agents), and methods for producing IL-17 receptor like polypeptides. Also provided for are methods for treatment, diagnosis, amelioration, or prevention of diseases with IL-17 receptor like polypeptides.Type: ApplicationFiled: October 28, 2010Publication date: June 30, 2011Applicant: Amgen Inc.Inventors: Eugene Medlock, Richard Yeh, Scott M. Silbiger, Gary S. Elliott, Hung Q. Nguyen, Shuqian Jing
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Patent number: 7969239Abstract: A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed.Type: GrantFiled: September 29, 2009Date of Patent: June 28, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Q. Nguyen, Thuan T. Vu, Anh Ly
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Publication number: 20110121799Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.Type: ApplicationFiled: January 10, 2011Publication date: May 26, 2011Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Sang Thanh Nguyen, Anh Ly, Hung Q. Nguyen, Wingfu Aaron Lau, Nasrin Jaffari, Thuan Trong Vu, Vishal Sarin, Loc B. Hoang