Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

Abstract: A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed.

Abstract: Disclosed is a composition of matter comprising an OSK1 peptide analog, and in some embodiments, a pharmaceutically acceptable salt thereof. A pharmaceutical composition comprises the composition and a pharmaceutically acceptable carrier. Also disclosed are DNAs encoding the inventive composition of matter, an expression vector comprising the DNA, and host cells comprising the expression vector. Methods of treating an autoimmune disorder and of preventing or mitigating a relapse of a symptom of multiple sclerosis are also disclosed.

Abstract: Disclosed is a DNA encoding a composition of matter of the formula (X1)a—(F1)d—(X2)b—(F2)e—(X3)c??(I) and multimers thereof, in which F1 and F2 are half-life extending moieties, and d and e are each independently 0 or 1, provided that at least one of d and e is 1; X1, X2, and X3 are each independently -(L)f-P-(L)g-, and f and g are each independently 0 or 1; P is a ShK peptide analog of no more than about 80 amino acid residues in length; L is an optional linker; and a, b, and c are each independently 0 or 1, provided that at least one of a, b and c is 1. A DNA encoding the ShK peptide analog is disclosed. Also disclosed are an expression vector comprising the DNA, and a host cell comprising the expression vector.

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract: Novel IL-17 like polypeptides and nucleic acid molecules encoding the same. The invention also provides vectors, host cells, selective binding agents, and methods for producing IL-17 like polypeptides. Also provided for are methods for the treatment, diagnosis, amelioration, or prevention of diseases with IL-17 like polypeptides, agonists, or antagonists thereof.

Abstract: An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array.

Abstract: Disclosed is a composition of matter comprising an OSK1 peptide analog, and in some embodiments, a pharmaceutically acceptable salt thereof. A pharmaceutical composition comprises the composition and a pharmaceutically acceptable carrier. Also disclosed are DNAs encoding the inventive composition of matter, an expression vector comprising the DNA, and host cells comprising the expression vector. Methods of treating an autoimmune disorder and of preventing or mitigating a relapse of a symptom of multiple sclerosis are also disclosed.

Abstract: Disclosed is a composition of matter of the formula (X1)a—(F1)d—(X2)b—(F2)e—(X3)c??(I) and multimers thereof, in which F1 and F2 are half-life extending moieties, and d and e are each independently 0 or 1, provided that at least one of d and e is 1; X1, X2, and X3 are each independently -(L)f-P-(L)g-, and f and g are each independently 0 or 1; P is a toxin peptide of no more than about 80 amino acid residues in length, comprising at least two intrapeptide disulfide bonds; L is an optional linker; and a, b, and c are each independently 0 or 1, provided that at least one of a, b and c is 1. Linkage to the half-life extending moiety or moieties increases the in vivo half-life of the toxin peptide, which otherwise would be quickly degraded. A pharmaceutical composition comprises the composition and a pharmaceutically acceptable carrier. Also disclosed are a DNA encoding the inventive composition of matter, an expression vector comprising the DNA, and a host cell comprising the expression vector.

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract: Disclosed is a composition of matter comprising an OSK1 peptide analog, and in some embodiments, a pharmaceutically acceptable salt thereof. A pharmaceutical composition comprises the composition and a pharmaceutically acceptable carrier. Also disclosed are DNAs encoding the inventive composition of matter, an expression vector comprising the DNA, and host cells comprising the expression vector. Methods of treating an autoimmune disorder and of preventing or mitigating a relapse of a symptom of multiple sclerosis are also disclosed.

Abstract: A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another.

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract: An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array.

Abstract: A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.