Patents by Inventor Hung-Sen Wang
Hung-Sen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757034Abstract: A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type.Type: GrantFiled: April 27, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang, Ho-Chun Liou
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Publication number: 20220254923Abstract: A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Inventors: HUNG-SEN WANG, YUN-TA TSAI, RUEY-HSIN LIU, SHIH-FEN HUANG, HO-CHUN LIOU
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Patent number: 11322609Abstract: A high-voltage device includes a substrate, a first well region disposed in the substrate, at least a first isolation, a frame-like gate structure over the first well region and covering a portion of the first isolation, a drain region in the first well region and separated from the frame-like gate structure by the first isolation, and a source region separated from the drain region by the first isolation and the frame-like gate structure. The first well region, the drain region and the source region include a first conductivity type, and the substrate includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.Type: GrantFiled: June 19, 2020Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hung-Sen Wang, Yun-Ta Tsai, Ruey-Hsin Liu, Shih-Fen Huang, Ho-Chun Liou
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Publication number: 20210167205Abstract: A high-voltage device includes a substrate, at least a first isolation in the substrate, a first well region, a frame-like gate structure over the first well region and covering a portion of the first isolation, a drain region in the first well region and separated from the frame-like gate structure by the first isolation, and a source region separated from the drain region by the first isolation and the frame-like gate structure. The first well region, the drain region and the source region include a first conductivity type, and the substrate includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.Type: ApplicationFiled: June 19, 2020Publication date: June 3, 2021Inventors: HUNG-SEN WANG, YUN-TA TSAI, RUEY-HSIN LIU, SHIH-FEN HUANG, HO-CHUN LIOU
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Patent number: 9553140Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.Type: GrantFiled: March 31, 2016Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung, Ho-Chun Liou
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Publication number: 20160218171Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Inventors: Hung-Sen WANG, Shih-Chi YANG, Kuo-Ching CHANG, Wei-Sho HUNG, Ho-Chun LIOU
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Patent number: 9331136Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.Type: GrantFiled: May 30, 2014Date of Patent: May 3, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung, Ho-Chun Liou
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Patent number: 9266714Abstract: A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.Type: GrantFiled: April 15, 2014Date of Patent: February 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
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Publication number: 20150349045Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Sen WANG, Shih-Chi YANG, Kuo-Ching CHANG, Wei-Sho HUNG, Ho-Chun LIOU
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Patent number: 8878312Abstract: An apparatus including a bypass structure for complementary metal-oxide-semiconductor (CMOS) and/or microelectromechanical system (MEMS) devices, and method for fabricating such apparatus, is disclosed. An exemplary apparatus includes a first substrate; a second substrate that includes a MEMS device; an insulator disposed between the first substrate and the second substrate; and an electrical bypass structure disposed in the insulator layer that contacts a portion of the first substrate, wherein the electrical bypass structure is electrically isolated from the MEMS device in the second substrate and any device included in the first substrate.Type: GrantFiled: August 1, 2011Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor manufacturing Company, Ltd.Inventors: Chia-Ming Hung, Hung-Sen Wang, Hsiang-Fu Chen, Te-Hsi Lee, Alex Kalnitsky, Wen-Chuan Tai, Kuei-Sung Chang, Yi Heng Tsai
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Patent number: 8879308Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.Type: GrantFiled: July 16, 2012Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shine Chung, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang, Hung-Sen Wang
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Publication number: 20140203421Abstract: A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.Type: ApplicationFiled: April 15, 2014Publication date: July 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Pao SHU, Chia-Ming HUNG, Wen-Chuan TAI, Hung-Sen WANG, Hsiang-Fu CHEN, Alex KALNITSKY
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Patent number: 8716852Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.Type: GrantFiled: February 17, 2012Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
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Publication number: 20130214400Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Pao SHU, Chia-Ming HUNG, Wen-Chuan TAI, Hung-Sen WANG, Hsiang-Fu CHEN, Alex KALNITSKY
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Patent number: 8451655Abstract: A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.Type: GrantFiled: February 2, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shine Chung, Hung-Sen Wang, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang
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Publication number: 20120281464Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shine Chung, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang, Hung-Sen Wang
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Publication number: 20120223613Abstract: An apparatus including a bypass structure for complementary metal-oxide-semiconductor (CMOS) and/or microelectromechanical system (MEMS) devices, and method for fabricating such apparatus, is disclosed. An exemplary apparatus includes a first substrate; a second substrate that includes a MEMS device; an insulator disposed between the first substrate and the second substrate; and an electrical bypass structure disposed in the insulator layer that contacts a portion of the first substrate, wherein the electrical bypass structure is electrically isolated from the MEMS device in the second substrate and any device included in the first substrate.Type: ApplicationFiled: August 1, 2011Publication date: September 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ming Hung, Hung-Sen Wang, Hsiang-Fu Chen, Te-Hsi Lee, Alex Kalnitsky, Wen-Chuan Tai, Kuei-Sung Chang, Yi Heng Tsai
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Patent number: 8223534Abstract: A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.Type: GrantFiled: January 14, 2010Date of Patent: July 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shine Chung, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang, Hung-Sen Wang
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Publication number: 20120127788Abstract: A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.Type: ApplicationFiled: February 2, 2012Publication date: May 24, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shine Chung, Hung-Sen Wang, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang
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Patent number: 8111544Abstract: A method of writing a magneto-resistive random access memory (MRAM) cell includes providing a writing pulse to write a value to the MRAM cell; and verifying a status of the MRAM cell immediately after the step of providing the first writing pulse. In the event of a write failure, the value is rewritten into the MRAM cell.Type: GrantFiled: November 13, 2009Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shine Chung, Hung-Sen Wang, Tao-Wen Chung, Chun-Jung Lin, Yu-Jen Wang