Patents by Inventor Hung-Sung Li
Hung-Sung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9402062Abstract: A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.Type: GrantFiled: May 12, 2008Date of Patent: July 26, 2016Assignee: MEDIATEK INC.Inventors: Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li
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Patent number: 8361757Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: GrantFiled: September 23, 2011Date of Patent: January 29, 2013Assignee: Mediatek Inc.Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
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Patent number: 8110876Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: GrantFiled: November 17, 2009Date of Patent: February 7, 2012Assignee: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Publication number: 20120009734Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: ApplicationFiled: September 23, 2011Publication date: January 12, 2012Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
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Patent number: 8049321Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: GrantFiled: March 2, 2009Date of Patent: November 1, 2011Assignee: Mediatek Inc.Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
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Patent number: 7995679Abstract: Provided are a method and system for digitizing a sensor model output signal. The system includes a filter, a demodulator coupled to the filter, a DC offset cancellation mechanism coupled to the demodulator, and an analog to digital converter (ADC). The ADC is directly coupled to the demodulator and the DC offset cancellation mechanism.Type: GrantFiled: April 27, 2005Date of Patent: August 9, 2011Assignee: Broadcom CorporationInventors: Sumant Ranganathan, Tom W. Kwan, Hung-Sung Li
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Patent number: 7948411Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.Type: GrantFiled: May 7, 2010Date of Patent: May 24, 2011Assignee: Mediatek Inc.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Patent number: 7830005Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.Type: GrantFiled: November 12, 2008Date of Patent: November 9, 2010Assignee: Mediatek Inc.Inventors: Chuan-Cheng Hsiao, Hung-Sung Li, I-Cheng Lin, Che-Yuan Jao
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Publication number: 20100225515Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.Type: ApplicationFiled: May 7, 2010Publication date: September 9, 2010Applicant: MEDIATEK INC.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Patent number: 7741984Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.Type: GrantFiled: September 24, 2008Date of Patent: June 22, 2010Assignee: Mediatek Inc.Inventors: Zwei-Mei Lee, Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li, Pao-Cheng Chiu
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Publication number: 20100128403Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: ApplicationFiled: November 17, 2009Publication date: May 27, 2010Applicant: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Publication number: 20100117207Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Inventors: Chuan-Cheng Hsiao, Hung-Sung Li, I-Cheng Lin, Che-Yuan Jao
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Publication number: 20100073209Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.Type: ApplicationFiled: September 24, 2008Publication date: March 25, 2010Applicant: MEDIATEK INC.Inventors: Zwei-Mei LEE, Kang-Wei HSUEH, Ya-Lun YANG, Hung-Sung LI, Pao-Cheng CHIU
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Publication number: 20090294944Abstract: A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die includes at least one bonding pad. The second semiconductor die includes a bonding pad module. The first conductive element is coupled between the bonding pad module of the second semiconductor die and the bonding pad of the first semiconductor die, and the second conductive element is coupled between the bonding pad module of the second semiconductor die and the semiconductor package component or the another semiconductor die, wherein the first semiconductor die is coupled to the semiconductor package component or the another semiconductor die via the bonding pad and the bonding pad module and the first and second conductive elements.Type: ApplicationFiled: March 2, 2009Publication date: December 3, 2009Inventors: Yin-Chao Huang, Shi-Bai Chen, Kang-Wei Hsueh, Hung-Sung Li
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Publication number: 20090289821Abstract: A pipeline analog-to-digital converter includes a sample and hold circuit; a plurality of multiplying digital-to-analog converters having a leading MDAC coupled to the sample and hold circuit; and an operational amplifier, shared by the sample and hold circuit and the leading MDAC. The shared operational amplifier configured to be used by the sample and hold circuit when the sample and hold circuit enters a hold phase and used by the leading MDAC when the sample and hold circuit enters a sample phase can greatly reduce the power consumption of the pipeline ADC.Type: ApplicationFiled: May 26, 2008Publication date: November 26, 2009Inventors: Hung-Sung Li, Ya-Lun Yang
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Patent number: 7622775Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.Type: GrantFiled: August 29, 2006Date of Patent: November 24, 2009Assignee: Broadcom CorporationInventors: Hung-Sung Li, Laurentiu Vasiliu
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Patent number: 7605654Abstract: A telescopic operational amplifier including a current source, an input stage, and a load stage is provided. The input stage is coupled to the current source and includes a group of input transistors for receiving an input voltage. The load stage is coupled to the input stage and includes a group of load transistors for outputting an output voltage. The threshold voltages of the group of input transistors are larger than that of the group of load transistors.Type: GrantFiled: March 13, 2008Date of Patent: October 20, 2009Assignee: Mediatek Inc.Inventors: Yung-Chih Yen, Hung-Sung Li
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Publication number: 20090231037Abstract: A telescopic operational amplifier including a current source, an input stage, and a load stage is provided. The input stage is coupled to the current source and includes a group of input transistors for receiving an input voltage. The load stage is coupled to the input stage and includes a group of load transistors for outputting an output voltage. The threshold voltages of the group of input transistors are larger than that of the group of load transistors.Type: ApplicationFiled: March 13, 2008Publication date: September 17, 2009Applicant: MEDIATEK INC.Inventors: Yung-Chih Yen, Hung-Sung Li
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Publication number: 20090021643Abstract: A digital television chip having a reduced layout size is disclosed, comprising a multiplexer, and first and second converting units. The multiplexer, according to a control signal, outputs one of S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs a CVBS Line-in Video signal to one of the first and second converting units, for reducing the size of the chip. The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.Type: ApplicationFiled: May 12, 2008Publication date: January 22, 2009Applicant: MEDIATEK INC.Inventors: Kang-Wei Hsueh, Ya-Lun Yang, Hung-Sung Li
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Patent number: 7477100Abstract: Provided are a method and system for demodulating a signal. The method includes receiving the signal along first and second signal paths within a demodulator having a common starting point. Impedance values along each of the paths are changed alternately in synchronism.Type: GrantFiled: April 27, 2005Date of Patent: January 13, 2009Assignee: Broadcom CorporationInventors: Sumant Ranganathan, Tom W. Kwan, Hung-Sung Li