Abstract: A circuit for reducing ground noise of video signals is provided. The circuit includes a current source, a plurality of resistors, an AC coupling circuit and a subtracting circuit. The resistors are used for outputting a first and second voltage levels corresponding to different voltages provided by the series-connected resistors. The AC coupling circuit is used for receiving a reference ground signal and coupling an AC component of the reference ground signal to generate the reference voltage level. The subtracting circuit is used for subtracting the first and second voltage levels from two video signals, respectively.

Abstract: Provided are a method and system for removing an offset direct current (DC) component from an input waveform. The method includes multiplying the input waveform with a demodulation waveform to produce a first differential current signal. An absolute value representation of the demodulation waveform is multiplied with a reference DC offset value to produce a second differential current signal. The first and second differential current signals are then differenced.

Abstract: A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The data sampling module converts the amplified input signal into a first data stream in accordance with at least one first sampling clock signal when the interface is configured in the first mode and to converts the amplified input signal into a second data stream in accordance with at least a second sampling clock signal when the interface is in a second mode. The clocking module generates the first sampling clock signals from a reference clock when the multi-protocol interface is in a first operational mode and generates the second sampling clock signals based on the reference clock when the interface is in the second operational mode.

Abstract: An input buffer for use in a differential operational amplifier is disclosed that regulates current through a main input differential pair while preventing output distortion and allowing high linearity. The input buffer includes a main input transistor pair that receives a voltage input, a tail current source, and a squeezable tail current source circuit including a single-ended self-biased folded feedback loop. These are configured such that current through the main input transistor pair is maintained as the voltage input varies. The folded feedback loop includes a folding transistor and a biasing current source that biases the folding transistor. The squeezable tail current source circuit also includes a replica transistor pair, a bias transistor, and a tail transistor pair. The biasing current source and folding transistor isolate the bias transistor and tail transistor pair from a drain voltage of the replica transistor pair, preventing output distortion and allowing high linearity.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: An input buffer for use in a differential operational amplifier is disclosed that regulates current through a main input differential pair while preventing output distortion and allowing high linearity. The input buffer includes a main input transistor pair that receives a voltage input, a tail current source, and a squeezable tail current source circuit including a single-ended self-biased folded feedback loop. These are configured such that current through the main input transistor pair is maintained as the voltage input varies. The folded feedback loop includes a folding transistor and a biasing current source that biases the folding transistor. The squeezable tail current source circuit also includes a replica transistor pair, a bias transistor, and a tail transistor pair. The biasing current source and folding transistor isolate the bias transistor and tail transistor pair from a drain voltage of the replica transistor pair, preventing output distortion and allowing high linearity.

Abstract: A squeezable tail current source for use in a differential operational amplifier is disclosed that regulates the current through a main input differential pair while preventing output distortion and allowing high linearity. The squeezable tail current source includes a first transistor pair that replicates a main input transistor pair, wherein both the first transistor pair and the main input transistor pair receive a common voltage input at their respective gates. The squeezable tail current source also includes a second transistor pair, a bias transistor, a first current source, a folding transistor, and a second current source that biases the folding transistor. These components are configured such that current through the main input transistor pair is maintained as the voltage input varies.

Abstract: Provided are a method and system for removing an offset direct current (DC) component from an input waveform. The method includes multiplying the input waveform with a demodulation waveform to produce a first differential current signal. An absolute value representation of the demodulation waveform is multiplied with a reference DC offset value to produce a second differential current signal. The first and second differential current signals are then differenced.

Abstract: Provided are a method and system for demodulating a signal. The method includes receiving the signal along first and second signal paths within a demodulator having a common starting point. Impedance values along each of the paths are changed alternately in synchronism.

Abstract: Provided are a method and system for digitizing a sensor model output signal. The system includes a filter, a demodulator coupled to the filter, a DC offset cancellation mechanism coupled to the demodulator, and an analog to digital converter (ADC). The ADC is directly coupled to the demodulator and the DC offset cancellation mechanism.

Abstract: A squeezable tail current source for use in a differential operational amplifier is disclosed that regulates the current through a main input differential pair while preventing output distortion and allowing high linearity. The squeezable tail current source includes a first transistor pair that replicates a main input transistor pair, wherein both the first transistor pair and the main input transistor pair receive a common voltage input at their respective gates. The squeezable tail current source also includes a second transistor pair, a bias transistor, a first current source, a folding transistor, and a second current source that biases the folding transistor. These components are configured such that current through the main input transistor pair is maintained as the voltage input varies.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

Abstract: A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

Abstract: Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.

Abstract: A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier is operably coupled to amplify a 1st formatted input signal or to amplify a 2nd formatted input signal to produce an amplified input signal. The data sampling module is operably coupled to convert the amplified input signal into a 1st data stream in accordance with at least one 1st sampling clock signal when the interface is configured in the 1st mode and to convert the amplified input signal into a 2nd data stream in accordance with at least a 2nd sampling clock signal when the interface is in a 2nd mode. The clocking module is operably coupled to generate the 1st sampling clock signals from a reference clock when the multi-protocol interface is in a 1st operational mode and generates the 2nd sampling clock signals based on the reference clock when the interface is in the 2nd operational mode.

Abstract: Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons.