Patents by Inventor Hung-Ta Lin
Hung-Ta Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150333129Abstract: A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Meng-Ku Chen, Hung-Ta Lin
-
Patent number: 9184289Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: GrantFiled: November 8, 2013Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
-
Publication number: 20150318214Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.Type: ApplicationFiled: August 14, 2014Publication date: November 5, 2015Inventors: Teng-Chun TSAI, Cheng-Tung LIN, Li-Ting WANG, Chih-Tang PENG, De-Fang CHEN, Hung-Ta LIN, Chien-Hsun WANG
-
Publication number: 20150318213Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.Type: ApplicationFiled: August 8, 2014Publication date: November 5, 2015Inventors: Teng-Chun TSAI, Li-Ting WANG, Cheng-Tung LIN, De-Fang CHEN, Chih-Tang PENG, Chien-Hsun WANG, Hung-Ta LIN
-
Patent number: 9166035Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: GrantFiled: September 12, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Ta Lin, Mao-Lin Huang, Li-Ting Wang, Chien-Hsun Wang, Meng-Ku Chen, Chun-Hsiung Lin, Pang-Yen Tsai, Hui-Cheng Chang
-
Publication number: 20150255575Abstract: The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.Type: ApplicationFiled: March 6, 2014Publication date: September 10, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, Hung-Ta Lin, Huicheng Chang
-
Patent number: 9130115Abstract: A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.Type: GrantFiled: February 24, 2014Date of Patent: September 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu, Hung-Ta Lin
-
Patent number: 9099311Abstract: A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate.Type: GrantFiled: January 31, 2013Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Huicheng Chang
-
Patent number: 9099388Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.Type: GrantFiled: October 21, 2011Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen
-
Publication number: 20150200258Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
-
Publication number: 20150194490Abstract: A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type.Type: ApplicationFiled: January 3, 2014Publication date: July 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
-
Publication number: 20150129938Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
-
Patent number: 9029246Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.Type: GrantFiled: July 30, 2013Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
-
Publication number: 20150069467Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: HUNG-TA LIN, MAO-LIN HUANG, LI-TING WANG, CHIEN-HSUN WANG, MENG-KU CHEN, CHUN-HSIUNG LIN, PANG-YEN TSAI, HUI-CHENG CHANG
-
Publication number: 20150035113Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.Type: ApplicationFiled: July 30, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
-
Publication number: 20140327091Abstract: A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.Type: ApplicationFiled: July 22, 2014Publication date: November 6, 2014Inventors: Hung-Ta LIN, Chu-Yun FU, Shin-Yeh HUANG, Shu-Tine YANG, Hung-Ming CHEN
-
Patent number: 8822290Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.Type: GrantFiled: January 25, 2013Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ta Lin, Meng-Ku Chen, Huicheng Chang
-
Patent number: 8809940Abstract: A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.Type: GrantFiled: April 9, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen
-
Patent number: 8803189Abstract: A circuit structure includes a substrate; a patterned mask layer over the substrate, wherein the patterned mask layer includes a plurality of gaps; and a group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layer includes a first portion over the mask layer and second portions in the gaps, wherein the III-V compound semiconductor layer overlies a buffer/nucleation layer.Type: GrantFiled: August 10, 2009Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou, Hung-Ta Lin
-
Publication number: 20140209974Abstract: A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Huicheng Chang