Abstract: This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

Abstract: A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.

Abstract: This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.

Abstract: A bubbler chamber assembly comprising one chamber or two or more chambers connected in series, all chambers being in substantially vertical orientation. A solid or liquid source of the compound is contained in the chamber or chambers. The ratio between the length of the chamber or combined length of chambers connected in series with respect to the direction of flow of the carrier gas through the chamber or chambers and the average diameter equivalent of the cross section of the chamber or chambers with respect to the direction of flow of the carrier gas through the chamber or chambers is not less than about 6:1.

Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.

Abstract: Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Abstract: Provided is a magnetic sensor for detecting a magnetic field. The magnetic sensor includes a magnetic layer of a closed loop shape; a pair of current terminals which face each other contacting with the closed loop and through which current is input/output; and a pair of voltage terminals which face each other contacting with the closed loop and from which output voltage is detected. Both an anisotropic magnetoresistance effect (AME) and a planar Hall effect (PHE) contribute to the output voltage and a hysteresis of the output voltage is eliminated by exchange coupling of a ferromagnetic layer by a ferromagnetic-antiferromagnetic layer structure and a ferromagnetic-metal-antiferromagnetic layer structure. Accordingly, it is possible to minimize a hysteresis due to a demagnetization factor of the closed loop, stabilize the output voltage of the magnetic sensor and enhance sensitivity.

Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.

Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.

Abstract: Methods and apparatus are provided for closing incisions within biological tissue. In one embodiment, a device and method are provided for suturing biological tissue, such as, for example, an organ or blood vessel. The suturing apparatus is particularly well suited for suturing an incision made in an artery, such as the femoral artery, following a catheterization procedure. The device eliminates the need to apply pressure to a patient's thigh for an extended period of time, and eliminates many of the complications and costs associated with the creation of a thrombus patch. In addition, the device comprises an improved handle portion which enables the physician to quickly and easily apply suture. The handle portion is very reliable and easy to manipulate. The suturing may be used in combination with existing catheter sheath introducers.

Abstract: Methods and apparatus are provided for closing incisions within biological tissue. In one embodiment, a device and method are provided for suturing biological tissue, such as, for example, an organ or blood vessel. The suturing apparatus is particularly well suited for suturing an incision made in an artery, such as the femoral artery, following a catheterization procedure. The device eliminates the need to apply pressure to a patient's thigh for an extended period of time, and eliminates many of the complications and costs associated with the creation of a thrombus patch. In addition, the device comprises an improved handle portion which enables the physician to quickly and easily apply suture. The handle portion is very reliable and easy to manipulate. The suturing may be used in combination with existing catheter sheath introducers.

Abstract: Data consistency in the context of information sharing requires maintenance of dependencies among information being shared. Transactional dependency ordering is implemented in a database system message queue, by associating a unique system commit time with each transactional message group. Read consistency is implemented in such a queue by allowing only messages with a fully determined order to be visible. A fully determined order is implemented through use of a high watermark, which guarantees that future transactions, for which messages are entering the queue, have commit times that are greater than the current high watermark. Therefore, only messages below the current high watermark are visible and can be dequeued, with no chance of other new messages enqueuing below the current high watermark.

Abstract: Embodiments of the present invention provide fine grain concurrency control for transactions in the presence of database updates. During operations, each transaction is assigned a snapshot version number or SVN. A SVN refers to a historical snapshot of the database that can be created periodically or on demand. Transactions are thus tied to a particular SVN, such as, when the transaction was created. Queries belonging to the transactions can access data that is consistent as of a point in time, for example, corresponding to the latest SVN when the transaction was created. At various times, data from the database stored in a memory can be updated using the snapshot data corresponding to a SVN. When a transaction is committed, a snapshot of the database with a new SVN is created based on the data modified by the transaction and the snapshot is synchronized to the memory.

Abstract: Embodiments of the present invention provide for batch and incremental loading of data into a database. In the present invention, the loader infrastructure utilizes machine code database instructions and hardware acceleration to parallelize the load operations with the I/O operations. A large, hardware accelerator memory is used as staging cache for the load process. The load process also comprises an index profiling phase that enables balanced partitioning of the created indexes to allow for pipelined load. The online incremental loading process may also be performed while serving queries.

Abstract: To export source tablespaces, an auxiliary database system is created and started with a minimum configuration. Copies of versions of the source tablespaces are restored from database backups to the auxiliary database system. A copy of a version of a tablespace is referred to herein as a tablespace instance. The tablespace instances restored from database backups are recovered to a particular point-in-time. A script is then generated. The script can be executed by a database server of the destination database to import the tablespace instances.

Abstract: A method and a Packet Data Service Node (PDSN) of restricting geographical use of a service for a mobile terminal (MT) in a packet data telecommunications network. The PDSN receives from an access node (AN), a registration request message having a cell information for requesting. The PDSN translates the cell information into a zone ID, stores the zone ID in a first table and sends to a AAA server, an access request message for authenticating the MT. PDSN further receives from the AAA server, an access accept message for authorizing the MT to receive packet data service, wherein the access accept message includes an allowance information. Afterwards the PDSN compares the allowance information with the zone ID. If the allowance information is different from the zone ID in the first table, the PDSN set up a filter for the MT and rejects packet data for the requested packet data service.

Abstract: Methods and apparatus to protect a protocol interface are described herein. In an example method, a driver request is received during an operation phase of firmware in a processor system. The driver request may be identified as a request associated with a violating condition of the protocol interface. Accordingly, the driver request is rejected.

Abstract: A method for providing a secure transmission of packet data on a plurality of network access modes in a packet data network. The UE-1 comprises a processing module for initiating communication with one or more receiving UE-2, operating a spread spectrum access (SS) middleware for communicating to a service application (SA) server for retrieving available access modes of the one or more receiving UE-2. The processing module retrieves available access modes for the one or more receiving UE-2, randomly breaks up an uplink transmission of packet data on multiple transmissions of packet data on available access modes of the UE-1 and sends packet data of the transmissions on available access modes of the UE-1.

Abstract: A process for depositing a substantially pure, conformal metal layer on one or more substrates through the decomposition of a metal-containing precursor. During this deposition process, the substrate(s) is maintained at a temperature greater than the decomposition temperature of the precursor while the surrounding atmosphere is maintained at a temperature lower than the decomposition temperature of the precursor. The precursor is dispersed within a transport medium, e.g., a vapor phase. The concentration of the metal-containing precursor(s) in the vapor phase, which also contains liquid therein, can be at a level to provide conditions at or near saturation for the metal precursor(s). In ensuring the aforementioned temperature control between the transport media and substrate, and in maintaining saturation conditions for the transport media, the quality of the deposited metal thin film is markedly improved and the production of by-product metal dust is greatly reduced or substantially eliminated.