Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.

Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

Abstract: A lens assembly and Augmented Reality (AR) glasses, including a waveguide substrate, a wiring layer, a protective layer, an eye tracking component, and a lens. The waveguide substrate includes a first surface. The wiring layer is disposed on the first surface. The protective layer is disposed on the first surface and covering the wiring layer. The eye tracking component is disposed in the protective layer and is electrically connected with the wiring layer for tracking position of an eyeball. The lens is connected to a side of the protective layer away from the waveguide substrate. The AR glasses includes a display device and two lens assemblies. The display device is positioned between the two lens assemblies for emitting image light to the waveguide substrates of the two lens assemblies.

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. The control logic identify a subset of memory blocks of one or more memory planes that pass a program count operation associated with a last programming level of the set of programming levels. The control logic further terminates execution of the programming operation on the one or more memory planes associated with the subset of memory blocks.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.

Abstract: A treatment method for waste water is provided. The method includes providing the waste water. The waste water includes monoethanolamine, and COD of the wastewater is in a range between 5000 mg/L and 30000 mg/L. The method further includes adjusting pH value of the wastewater to be not smaller than 11.5; transferring the wastewater to a tank, and controlling a temperature of the tank to 20° C. to 32° C.; and adding hydrogen peroxide solution and ozone into the tank, thereby obtaining degraded waste water. By controlling treatment condition of the waste water, the waste water with the monoethanolamine and high COD can be degraded by using the hydrogen peroxide solution and the ozone.

Abstract: An electronic device is provided. The electronic device includes a semiconductor die. The semiconductor die has a first region of a first functional cell close to the peripheral edge of the semiconductor die. The semiconductor die includes a semiconductor substrate, a first signal bump, and a first power bump. The first signal bump and the first power bump are disposed on opposite surfaces of the semiconductor substrate and electrically connected to the first functional cell. The first signal bump and the first power bump both overlap the first region.

Abstract: Disclosed is a liquid crystal display (LCD) device, including an LCD panel and a light-emitting diode (LED) light board. The LCD panel has a display area and a peripheral area located on at least one side of the display area. The LED light board overlaps the LCD panel in a normal direction of a light-emitting surface of the LCD panel. The LED light board includes a circuit substrate, multiple LEDs, and a resin layer. The circuit substrate overlaps the display area and the peripheral area in the normal direction of the light-emitting surface. The LEDs are arrayed on the circuit substrate. The LEDs overlap the display area in the normal direction of the light-emitting surface. The resin layer covers the circuit substrate and overlaps the display area and the peripheral area in the normal direction of the light-emitting surface.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: Cleaning tools for cleaning the pull cable of an ingot puller apparatus and methods for cleaning the pull cable are disclosed. The cleaning tool includes a chamber for receiving the pull cable. Pressurized fluid is discharged through one or more nozzles to detach debris from the pull cable. The fluid and debris are collected in an exhaust plenum of the cleaning tool and are expelled through an exhaust tube. The cleaning tool includes one or more guides that guide the cleaning tool in an upper segment of the ingot puller apparatus.

Abstract: A method for manufacturing a keycap includes a plastic injection step that involves forming a keycap preform; a coating layer forming step that involves spraying a surface paint material onto a processing surface of the keycap preform to form a surface paint coating layer, which has an engraved marking portion; a protection layer forming step that involves spraying a protection material onto the surface paint coating layer to form a first protection layer; a laser engraving step that involves removing the engraved marking portion; and a screen printing step that involves forming a second protection layer on the processing surface.

Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: The disclosure provides an electrical apparatus, including a substrate, a plurality of gate driver units and a plurality of gate lines. The gate driver units are disposed on the substrate. The gate lines are disposed on the substrate. Each of the gate lines is respectively electrically connected to the corresponding gate driver unit. Each of the gate lines is configured to transmit a respective gate signal. The gate lines include a first gate line and a second gate line. The first gate line and the second gate line are configured to transmit the respective gate signals at a same time.

Abstract: The present invention generally relates to a hydroponic culture medium and a hydroponic planting system, more particularly to a Houttuynia cordata hydroponic culture medium, a Houttuynia cordata hydroponic planting system, Houttuynia cordata extracts, a method, and applications thereof. The Houttuynia cordata hydroponic culture medium includes a plant fertilizer and a Houttuynia cordata growth-promoting additive. The Houttuynia cordata growth-promoting additive is selected from the group consisting of: vitamin B complex, seaweed essence, amino acid, microorganism, and a combination thereof. An electronic conductivity of the Houttuynia cordata hydroponic culture medium is between 0.4 ms/cm and 2.0 ms/cm.

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.