Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: Embodiments of the present disclosure relates to an optical lens and a HUD using the optical lens. The optical lens includes a first lens, a second lens, and an optical waveguide. The first lens includes at least two focal parts with different powers. Since the HUD utilizes the optical lens, the user can maintain a comfortable viewing effect when wearing the HUD for a long time.

Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.

Abstract: A bonding method for using a bonding apparatus includes: transporting and reeling a carrier tape which is packaged with an adhering component, on a pressing assembly, and bending the carrier tape through a bending member to be divided into an input section and an output section; driving a roller to indirectly press and abut a front end of the adhering component to bring the adhering component into contact with a bonding start point a base component; and rolling the roller over the carrier tape to attach the adhering component to the bonding area while moving the bending member to indirectly scrape the adhering component from the carrier tape so as to firmly attach the adhering component to the base component without generation of air bubbles.

Abstract: A bonding device includes a first carrying module for a tape assembly to be disposed thereon and reeling a carrier tape and a cover tape, a driving module disposed to drive an up-down movement and a rotation of the first carrying module, a second carrying module movably disposed on the first carrying module, and a bonding module disposed on the second carrying module. The bonding module includes a bending member on and through which a carrier tape is reeled and bent to be divided into an input section and an output section. The bending member is moved together with a roller, during rolling of the roller, to indirectly scrape an adhering component from the carrier tape so as to facilitate attachment of the adhering component to the base component.

Abstract: A video processing device for virtual reality is provided. The video processing device includes a video input mechanism configured to receive a first and a second original video obtained from a first camera device; a video processing mechanism in transmission connecting to the video input mechanism, the video processing mechanism includes a first video processing unit configured to adjust the first and the second original video to a first video and a second video, the first video processing unit is configured to further combine the first video and the second video into a third video having a 16:9 aspect ratio, and dimensions of the third video being a total of those of the first and the second video; and a video output mechanism in transmission connecting to the video processing mechanism through a physical wire. A video generating system for virtual reality is also provided.

Abstract: A display apparatus includes a driving backplane, a first bank layer, light-emitting elements, a second bank layer, light adjusting patterns, a light-shielding pattern layer and color filter patterns. The color filter patterns includes first color filter patterns having the same color. The light-emitting elements include first light-emitting elements respectively overlapping the first color filter patterns. The light adjusting patterns include first color conversion patterns respectively overlapping the first color filter patterns. A center wavelength of one of the first light-emitting elements is greater than a center wavelength of another one of the first light-emitting elements, and a thickness of one of the first color conversion patterns is greater than a thickness of another one of the first color conversion patterns.

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes receiving a workpiece having gate structures over channel regions on a substrate and source/drain (S/D) features adjacent to the channel regions. The method then forms tungsten S/D contacts over the S/D features in a first ILD layer by a first selective bottom-up metal growth process. The method forms tungsten S/D vias over the tungsten S/D contacts in a second ILD layer by a second selective bottom-up metal growth process. And after forming the tungsten S/D vias, the method forms tungsten gate vias over the gate structures in the first and the second ILD layer. The forming of the tungsten gate vias includes forming a tungsten seed layer by physical vapor deposition (PVD), and depositing tungsten directly on horizontal and sidewall surfaces of the tungsten seed layer by chemical vapor deposition (CVD).

Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.

Abstract: An extreme ultra violet (EUV) light source apparatus includes an excitation laser inlet port configured to receive an excitation laser, and a first mirror configured to reflect the excitation laser that passes through a zone of excitation. A metal droplet is irradiated by the excitation laser.

Abstract: Microwave heating of debris collecting vanes within the source vessel of a lithography apparatus is used to accomplish uniform temperature distribution in order to reduce fall-on contamination and formation of clogs on the inner and outer surfaces of the vanes.

Abstract: A mask includes a first surface and a second surface opposite to the first surface, and has a total etching area and clearance areas. The mask has vias in the total etching area, and each via communicates the first surface with the second surface. The clearance areas are arranged in the total etching area, and the vias surround each clearance area. Each clearance area further has a through hole therein communicating the first surface with the second surface. Each clearance area is in a shape of a circle or a polygon. When each interior angle of the polygon is less than 120 degrees, the clearance area further comprises a first clearance region and a second clearance region surrounded by the first clearance region, and the mask has a plurality of etched grooves in the first clearance region. The disclosure further provides a manufacturing method of a mask.

Abstract: A system for monitoring and controlling an EUV light source includes a first temperature sensor, a signal processor, and a process controller. The first temperature sensor includes a portion inserted into a space surrounded by a plurality of vanes through a vane of the plurality of vanes, and obtains an ambient temperature that decreases with time as a function of tin contamination coating on the inserted portion. The signal processor determines an excess tin debris deposition on the vane based on the obtained chamber ambient temperature. The process controller activates a vane cleaning action upon being informed of the excess tin debris deposition by the signal processor, thereby improving availability of the EUV light source tool and reducing risks of tin pollution on other tools such as a reticle.

Abstract: An extreme ultra violet (EUV) light source apparatus includes a metal droplet generator, a collector mirror, an excitation laser inlet port for receiving an excitation laser, a first mirror configured to reflect the excitation laser that passes through a zone of excitation, and a second mirror configured to reflect the excitation laser reflected by the first mirror.

Abstract: An electronic device with short frame time length is provided. The electronic device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and two first integrated circuits. The plurality of first signal lines are disposed on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. The plurality of second signal lines are disposed on the substrate. The plurality of second signal lines are disposed alternately with the plurality of first signal lines. The two first integrated circuits are bonded on the substrate. Each of the two first integrated circuits are electrically connected to the first group of signal lines and the second group of signal lines. The first group of signal lines and the second group of signal lines are disposed alternately in columns.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A method includes forming a first electrode, and depositing a dielectric layer over the first electrode. The dielectric layer has a first dielectric constant and a first thickness. A dielectric capping layer is deposited over the dielectric layer. The dielectric capping layer has a second dielectric constant higher than the first dielectric constant, and a second thickness smaller than the first thickness. The method further includes forming a second electrode over the dielectric capping layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.