Abstract: An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas, and the laterals of the leads between the top surfaces and the bottom surfaces. A plurality of cavities are formed in the bottom of the encapsulant to expose the corresponding and embedded ball-placement areas. The lips have a plurality of internal sides exposed inside the cavities.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract: The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the first inner leads is greater than that of the second inner leads; and a plurality of semiconductor chip devices. The active surface of each chip faces upward and chips are misaligned to form offset stacked structure, wherein the semiconductor chip device stacked uppermost is fixedly connected under said first inner leads, and the plurality of semiconductor chip devices are electrically connected to the first inner leads and the second inner leads on the same side edge.

Abstract: A leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow.

Abstract: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A packaging apparatus is disclosed having a substrate with an interior area and a peripheral area. The substrate is configured to have an integrated circuit chip bonded to an adhesion structure located substantially within the interior area of the substrate. The substrate is further configured to have the integrated circuit chip electrically coupled to either the interior area on a distal surface of the substrate or the peripheral area on a proximate side of the substrate through a conductive structure. The adhesion structure includes a bonding area configured to accept an adhesive layer formed between the integrated circuit chip and the interior area of the substrate, and at least one protrusion structure being formed substantially within the bonding area of the substrate and configured to define a gap between the integrated circuit chip and the interior area of the substrate.

Abstract: A chip package structure includes a circuit substrate, a chip, an adhesive layer, conductive wires, and a molding compound. The circuit substrate has a first, a second surface, a slot, and a solder mask layer disposed on the first surface. The solder mask layer has a first and a second opening located at two sides of a longitude direction of the slot. The chip is disposed on the first surface and covers at least a portion of the slot. The adhesive layer is disposed between the chip and the circuit substrate and located at two sides of each of the slot, the first opening, and the second opening. The conductive wires connect the chip and the second surface through the slot. The molding compound covers the chip, the adhesive layer, and the conductive wires and the molding compound is further filling into the slot, the first and the second opening.

Abstract: An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed.

Abstract: A chip package structure includes a circuit substrate, a chip, an adhesive layer, conductive wires, and a molding compound. The circuit substrate has a first, a second surface, a slot, and a solder mask layer disposed on the first surface. The solder mask layer has a first and a second opening located at two sides of a longitude direction of the slot. The chip is disposed on the first surface and covers at least a portion of the slot. The adhesive layer is disposed between the chip and the circuit substrate and located at two sides of each of the slot, the first opening, and the second opening. The conductive wires connect the chip and the second surface through the slot. The molding compound covers the chip, the adhesive layer, and the conductive wires and the molding compound is further filling into the slot, the first and the second opening.

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract: A BGA package primarily includes a plurality of leads from a leadless lead frame, a chip, and a die-attaching layer. The chip is electrically connected to the leads by a plurality of bonding wires. Solder balls are disposed at the ball placing regions of the leads. Encapsulant encapsulates the chip, the die-attaching layer, and the top surfaces, the bottom surfaces, and the sides of the leads so that the ball placing regions are embedded inside the encapsulant. A plurality of cavities are formed in the encapsulant to expose the corresponding ball placing regions to resolve the solderability of the solder balls and to enhance the stability and reliability of wire bonding and solder ball placing. In one embodiment, a die-attaching layer between the chip and the leads is patterned for elastically supporting the solder balls and for wire bonding.

Abstract: The present invention provides a chip-stacked structure, comprising: a substrate with a plurality of terminals and a chip-stacked structure formed by a plurality of stacked chips and fixedly connected to the substrate. Wherein an active surface of each chip in the chip-stacked structure is provided with a plurality of pads and the back surface of each chip is provided with an insulation layer. The plurality of chips is connected by an adhesive layer provided between the active surface of one chip and the insulation layer on the back surface of another chip and thus the chip-stacked structure is formed. The plurality of pads is electrically connected to the plurality of terminals on the substrate with a plurality of metal wires.