Abstract: A multi-chip stacked package is revealed, primarily comprising a spacer pad and a plurality of leads of a lead frame, a first chip, a second chip, and an encapsulant. A plurality of first electrodes are formed on the active surface of the first chip below the spacer pad and are electrically connected to one surfaces of the leads. A plurality of second electrodes are formed on the active surface of the second chip above the spacer pad and are electrically connected to the same surfaces of the leads. The encapsulant encapsulates the spacer pad, parts of the leads, the first chip, and the second chip where the active surface of the first chip is attached to the bottom surface of the spacer pad and the back surface of the second chip to the top surface of the spacer pad. Moreover, the spacer pad does not cover the first electrodes of the first chip for wire-bonding to achieve multi-chip stacking with a reduced overall package thickness.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: Manufacturing processes of a leadframe-based BGA package and a leadless leadframe implemented in the processes are disclosed. The leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow. Moreover, mold flash can easily be detected and removed. The overall package cost can be reduced.