Patents by Inventor Hung-Wei Chen

Hung-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210407947
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Chi CHEN, Hsun-Ying HUANG, Chih-Ming LEE, Shang-Yen WU, Chih-An YANG, Hung-Wei HO, Chao-Ching CHANG, Tsung-Wei HUANG
  • Publication number: 20210408362
    Abstract: A piezoelectric actuator includes a square suspension plate, an outer frame, a plurality of brackets and a square piezoelectric ceramic plate. The outer frame is arranged around the suspension plate. A second surface of the outer frame and a second surface of the suspension plate are coplanar with each other. Each of the plurality of brackets has two ends, a first end is perpendicular to and connected with the suspension plate, and a second end is perpendicular to and connected with the outer frame for elastically supporting the suspension plate. Each bracket has a length in a range between 1.22 mm and 1.45 mm and a width in a range between 0.2 mm and 0.6 mm. A length of the piezoelectric ceramic plate is not larger than a length of the suspension plate. The piezoelectric ceramic plate is attached on a first surface of the suspension plate.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 30, 2021
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan MOU, Shih-Chang CHEN, Jia-Yu LIAO, Hung-Hsin LIAO, Che-Wei HUANG, Chi-Feng HUANG, Yung-Lung HAN, Chun-Yi KUO, Wei-Ming LEE
  • Publication number: 20210397820
    Abstract: A driver login device includes: a network communication unit in communication with the server via a network; an image pickup device capturing a target to obtain a login data; an image processing unit electrically coupled to the image pickup unit, and receiving and processing the login data to obtain a digital data; and a central processing unit electrically coupled to the network communication unit, the image pickup device and the image processing unit. The central processing unit, by way of the network communication unit, receives the data of the driver from the server via the network, controls the image pickup device to capture the target, comparing the digital data with the data of the driver to generate a comparing result, and by way of the network communication unit, transmitting the comparing result back to the server via the network.
    Type: Application
    Filed: March 8, 2021
    Publication date: December 23, 2021
    Inventors: TsungHsien WU, Hung-Pin CHEN, Chia-Wei HUANG, Michael Andrew Fox
  • Patent number: 11204545
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Cheng Hsu, Ching-Huang Chen, Hung-Yi Tsai, Ming-Wei Chen, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11065617
    Abstract: A flow passage design for multi-reaction biological detection includes a first temporary tank, a second temporary tank, a first microchannel, and a second microchannel. The first temporary tank is configured to temporarily store a first liquid in an initial state. The second temporary tank is configured to temporarily store a second liquid in the initial state. The first microchannel is located upstream of the first temporary tank. The first microchannel has an outlet end and an inlet end, respectively connecting to the first temporary tank and the second temporary tank. The second microchannel is located downstream of the first temporary tank and connects to the first temporary tank. In the initial state, a portion of the first liquid enters the second microchannel, the outlet end of the first microchannel is covered by the first liquid, and the inlet end of the first microchannel is covered by the second liquid.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 20, 2021
    Assignee: SKYLA CORPORATION HSINCHU SCIENCE PARK BRANCH
    Inventors: Chia-Chun Wei, Hung-Wei Chen, Ping-Hsing Ho
  • Publication number: 20210216114
    Abstract: An electronic device includes a chassis housing one or more electronic components, a module configured to be inserted into a channel defined by the chassis, and an alignment mechanism disposed in the channel. The alignment mechanism has a body portion that defines an aperture. When the module is initially inserted into the channel in a first orientation, a first portion of the module passes over the aperture and compresses the body portion of the alignment mechanism along a first axis, to allow the module to be fully inserted into the channel. When the module is initially inserted into the channel in a second orientation, a second portion of the module passes through the aperture and does not compress the body portion of the alignment mechanism along the first axis, to prevent the module from being fully inserted into the channel.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Inventors: Yaw-Tzorng TSORNG, Hung-Wei CHEN, Chun CHANG, Ming-Lung WANG
  • Publication number: 20210159693
    Abstract: The present invention provides an on-chip surge protection circuit, including a low voltage rail, a negative transmitter differential output, a positive transmitter differential output, and a surge protection component. The surge protection component includes a first end, a second end, and a control end. The first end is connected to the transmitter differential output N. The second end is connected to the transmitter differential output P. The control end is connected to the low voltage rail.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 27, 2021
    Inventors: Cheng-Hsu WU, Cheng-Chieh HSU, Che-Yuan JAO, Hung-Wei CHEN, Tsung-Hsien HSIEH
  • Patent number: 10826449
    Abstract: Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 3, 2020
    Assignee: HYCON TECHNOLOGY CORP.
    Inventors: Po-Yin Chao, Hung-Wei Chen, Shui-Chu Lee
  • Patent number: 10818653
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 27, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Shang-Chuan Pai, Wei-Chung Wu, Szu-Chi Chen, Sheng-Chih Chuang, Yin-Ting Lin, Pei-Chun Yu, Han-Pei Liu, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Publication number: 20200300897
    Abstract: Disclosed is a sensor with compensation circuit for compensating offset by use of a switching circuit. The sensor has two operation modes for generating two output voltages, respectively. Offset is compensated by adding the two output voltages, and magnitude of the offset is calculated by subtracting the two output voltages. A noise threshold is set for checking if the circuit is affected by interference. When the circuit is affected by interference, the adding result of the two output voltages will be larger than the noise threshold, the output data will be hold and not updated, then a reminding signal will be issued to show that the circuit is affected by interference, and the output data flickers on a display unit when the adding result of the two output voltages is larger than the noise threshold for showing the circuit is affected by interference.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Po-Yin CHAO, Hung-Wei CHEN, Shui-Chu LEE
  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10715172
    Abstract: Disclosed is an analog-to-digital converter with an adjustable operation frequency for noise reduction. The operation frequency of the analog-to-digital converter is adjustable, and if an input signal or a circuit is affected by a noise, the noise can be reduced by spreading the frequency distribution of the noise. A clock generator generates a clock signal for controlling the operation frequency of the analog-to-digital converter. Additionally, a clock controller receives a setting signal and a counting signal, controls the clock generator, and adjusts the frequency of the clock signal. In addition, a counter counts the number of periods of the clock signal, and generates the counting signal. Furthermore, a selecting signal makes the frequency of the clock signal gradually increase or decrease with time, thereby allowing change rate or change amount of the frequency of the clock signal to be adjustable.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 14, 2020
    Assignee: HYCON TECHNOLOGY CORP
    Inventors: Po-Yin Chao, Hung-Wei Chen, Shui-Chu Lee
  • Publication number: 20200186109
    Abstract: Disclosed is a high accurate measurement circuit, and the feature is using bias switching circuit for compensating front end offset, and the back end offset of amplifier is also cancelled. In the real measurement environment, offset exists in the amplifier of the measurement circuit has, and non-ideal effects also exist in the interface between measurement terminal and the measurement circuit, such as leakage current of chip package pins or mismatch of the circuit. The above non-ideal effects belong to front end offset and cannot be compensated by the prior arts. The disclosed structure uses the bias switch circuit and uses different switching method in the two measurement timings. By subtracting the measurement results for the two measurement timings, the front end offset is compensated, and the back end offset of the amplifier is also cancelled.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 11, 2020
    Inventors: PO-YIN CHAO, HUNG-WEI CHEN, SHUI-CHU LEE
  • Publication number: 20200098740
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 26, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Li-Fan CHEN, Chih-Hsuan LIN, Yu-Kai WANG, Hung-Wei CHEN, Ching-Wen WANG, Ting-You LIN, Chun-Chih CHEN
  • Patent number: 10589271
    Abstract: A blood plasma and blood cell separation device includes a first body, a blood plasma separation membrane and a second body. The first body has an injection port. The blood plasma separation membrane is disposed on the first body. The second body is movably assembled to the first body and has a collecting stage. The collecting stage has a collecting surface and a sampling recess on the collecting stage. When a blood enters the blood plasma separation membrane from the injection port of the first body, a blood plasma in the blood plasma separation membrane is separated by a capillary force between the collecting stage of the second body and the blood plasma separation membrane, and the blood plasma enters in the sampling recess by a relative movement between the first body and the second body.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: March 17, 2020
    Assignee: SKYLA CORPORATION HSINCHU SCIENCE PARK BRANCH
    Inventors: Ping-Hsing Ho, Chia-Chun Wei, Hung-Wei Chen
  • Patent number: 10523002
    Abstract: An electrostatic discharge (ESD) protection circuit is provided. A detector is coupled between a first input-output pad and a second input-output pad and detects the voltage levels of the first and second input-output pads to generate a detection signal. A inverter generates a control signal according to the detection signal. A control element is coupled between the first input-output pad and a first node. A current release element is coupled between the first node and the second input-output pad. When the detection signal is at a specific level, the control element and the current release element provide a discharge path to release an ESD current from the first input-output pad to the second input-output pad. When the detection signal is not at the specific level, the control element and the current release element do not provide a discharge path.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 31, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Jung-Tsun Chuang, Chieh-Yao Chuang, Hung-Wei Chen
  • Patent number: 10456781
    Abstract: The present invention provides a fluid inspection device comprising at least one channel including a top channel surface and a bottom channel surface, and a first spacing formed therebetween; at least one chamber communicating with the at least one channel from which a fluid flows into the at least one chamber and including a top chamber surface, a bottom chamber surface and a fluid-filling area and a through opening communicating with the at least one chamber and the outside. A second spacing is formed between the top chamber surface of at least one portion of the fluid-filling area and a corresponding bottom chamber surface thereof, wherein the second spacing is smaller than the first spacing. The fluid inspection device prevents bubbles from producing in the chamber and obstructing the inspection and further allows less required fluid amount in the chamber.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 29, 2019
    Assignee: SKYLA CORPORATION HSINCHU SCIENCE PARK BRANCH
    Inventors: Szu-Hsien Ho, Chia-Chun Wei, Hung-Wei Chen
  • Publication number: 20190208956
    Abstract: A food heating device with multilayer shelf includes a base, one or more shelf support, a first side wall member, a second side wall member, a bottom cover member, a middle cover member, and a top lamp bracket. There are two or more layers of heating rollers between the first side wall member and the second side wall member. The bottom cover member and the middle cover member are disposed above bottom heating rollers and middle heating rollers. Each of the cover members at different layers has a cover body. The cover body covers foods on the heating rollers. In addition, one or more lamp bodies can be provided. The food heating device with multilayer shelf is capable of increasing space for exhibition of foods and also increasing overall brightness by adding the lamp bodies.
    Type: Application
    Filed: October 30, 2018
    Publication date: July 11, 2019
    Inventors: Hung-Wei Chen, Hsiu-Chuan Chang, Kuo-Yi Liu, Li-Ping Yang, Chun-Ling Tai
  • Publication number: 20190181135
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
  • Patent number: D887768
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 23, 2020
    Assignee: PRESIDENT CHAIN STORE CORP.
    Inventors: Hung-Wei Chen, Hsiu-Chuan Chang, Kuo-Yi Liu, Li-Ping Yang, Chun-Ling Tai