Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

Abstract: A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

Abstract: A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of <100> and <110>; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of <110> and <100> different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

Abstract: Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region.

Abstract: A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 ?. Interfacial layers are formed between the first and the second Schottky barrier regions.

Abstract: A cassette stocker and method of forming the same. The cassette stocker comprises a housing, at least one operation device, and a transferring device. The housing comprises a plurality of openings. The operation device is disposed corresponding to the openings and storing a cassette. The transferring device is disposed in the housing, retrieving and transferring the cassette stored in the operation device via the openings.

Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

Abstract: A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and the gate electrode; a source doped with a first type of dopant substantially under the source gate spacer wherein the source has a horizontal distance from a first edge of the gate electrode; a drain doped with the opposite type of the source substantially under the drain spacer and substantially aligned horizontally with a second edge of the gate electrode; a source silicide adjacent the source; and a drain silicide adjacent the drain.

Abstract: A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.

Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

Abstract: Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

Abstract: Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride—silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

Abstract: A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

Abstract: A semiconductor-on-insulator device includes a silicon active layer with a <100> crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a <110> crystal direction. Transistors oriented on a <100> direction are formed on the silicon active layer.

Abstract: An automatic material handing system (AMHS). The AMHS comprises a rail, an overhead shuttle (OHS) and a stocker. The OHS moves on the rail. An in/out port (I/O port) is disposed in the stocker. The rail passes through the stocker and enters the I/O port. When the OHS is in the I/O port, a transport device places goods directly into the OHS.