Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

Abstract: Disclosed in the present disclosure is a locking bracket and a chassis. The locking bracket includes a locking base and a locking block. The locking base is fixedly connected to the chassis, and the locking block is movably connected to the locking base along a preset path to switch the locking block to the locked state when installing the functional module into the chassis. The clamping groove can clamp the limiting portion of the installing bracket that covers and fixes the functional module to fix its position, thereby improving the problem of component detachment caused by vibration, shaking, or impact during transportation of the chassis. When it is necessary to remove the functional module from the chassis, the locking block is moved along the preset path to switch from the locked state to the unlocked state.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Abstract: A foldable device may include a foldable layer and a hinge mechanism. The hinge mechanism may include at least one synchronizing module, at least one torsion module, and a cover module. The at least one synchronizing module may include a synchronizing gear assembly including a first linking gear in meshed engagement with a first rotating link, a second linking gear in meshed engagement with a second rotating link, and at least one intermediate gear in meshed engagement with the first linking gear and the second linking gear. The first rotating link may be coupled to a first housing of a computing device and the second rotating link may be coupled to a second housing of the computing device. The meshed engagement of the first and second rotating links may provide of synchronized, symmetric movement of the first and second housings about a central axis of the computing device.

Abstract: An assembly for securing an electrical component to a server is disclosed. The assembly includes a structural case configured to receive and secure in place an electrical component for the server; a pair of rail holders mounted to the structural case, each rail holder of the pair of rail holders having a plurality of mounting holes that includes a first hole and a second hole; and a pair of latches, each latch of the pair of latches being movably mounted to a respective one of the pair of rail holders, each latch having a finger end that is coupled to a hook end via a bridge portion. The finger end and the hook end are inserted, respectively, into the first hole and the second hole of the respective one of the pair of rail holder, and independently and flexibly move relative to the bridge portion in response to applied pressure.

Abstract: A method for a UE for performing a HARQ feedback operation for an SPS transmission is disclosed.

Abstract: Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

Abstract: Provided is a micro-roughened electrodeposited copper foil, which comprises a micro-rough surface and multiple copper nodules. The micro-roughened electrodeposited copper foil has an Sdr of 0.01 to 0.08. With the surface characteristics, the electron path distance can be shortened, such that the micro-roughened electrodeposited copper foil can reduce the insertion loss of the copper clad laminate at high frequencies and have the desired peel strength.

Abstract: Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

Abstract: An eye-bolt assembly includes an eye bolt and a base portion. The eye bolt includes a ring portion, a stem portion, and at least one winged extension. The ring portion is attached a first end of the stem portion. The at least one winged extension is attached to a second end of the stem portion. The base portion receives and securely locks the eye bolt therein. The base portion includes a collar and a platform secured to the collar. The collar forms a first aperture therein. The platform forms a second aperture therein. The platform includes a spring being located at least partially within the second aperture. A first end of the spring is attached to the platform. The second aperture formed in the platform is in spaced communication with the first aperture formed in the collar.

Abstract: A UE and a method for handling HARQ-ACK codebook transmission are provided. The method includes receiving, from a BS, a first configuration for unicast configuration for unicast SPS PDSCH, a second configuration for multicast SPS PDSCH, and a third configuration for unicast PDSCH; receiving, from the BS, a PUCCH configuration for unicast; receiving DCI scheduling a unicast PDSCH; determining a Type-1 HARQ-ACK codebook corresponding to the unicast PDSCH based on the first configuration for unicast SPS PDSCH, the second configuration for multicast SPS PDSCH, and the third configuration for unicast PDSCH; and transmitting, to the BS, the Type-1 HARQ-ACK codebook corresponding to the unicast PDSCH in a first slot.

Abstract: A method performed by a UE for wireless communications is provided. The method includes determining whether a first HARQ process of a first PUSCH duration of a first configured uplink grant is occupied by a dynamic uplink grant indicating a second PUSCH duration, and in a case that the first HARQ process of the first PUSCH duration is occupied by the dynamic uplink grant indicating the second PUSCH duration, determining whether the first PUSCH duration is prioritized over the second PUSCH duration based on a set of rules for determining priorities for the first PUSCH duration and the second PUSCH duration, and when the first PUSCH duration is prioritized over the second PUSCH duration, performing transmission on the first PUSCH duration, and starting or restarting a first configured grant timer corresponding to the first HARQ process of the first PUSCH duration during the first PUSCH duration.

Abstract: Provided is a micro-roughened electrodeposited copper foil, which comprises a micro-rough surface and multiple copper nodules. The micro-roughened electrodeposited copper foil has an Rlr value of 1.05 to 1.60, or an Sdr of 0.01 to 0.08. With the surface characteristics, the electron path distance can be shortened, such that the micro-roughened electrodeposited copper foil can reduce the insertion loss of the copper clad laminate at high frequencies and have the desired peel strength.

Abstract: A touch display device includes a reflective display module, a touch sensing layer, a light guide member, a ground shielding layer, and a first adhesive layer. The touch sensing layer is disposed on a display surface of the reflective display module, and the light guide member is disposed between the reflective display module and the touch sensing layer. The ground shielding layer is in contact with the light guide member and located between the light guide member and the touch sensing layer. The ground shielding layer electrically connects to one of the reflective display module and the touch sensing layer to electrically connect to a ground potential through the one of the reflective display module and the touch sensing layer. The first adhesive layer is disposed between the light guide member and the reflective display module, and is located between the ground shielding layer and the reflective display module.

Abstract: A method for delay information reporting is provided. The method receives a threshold via RRC signaling. The method determines whether at least one of delay budgets of one or more packets buffered in a first logical channel group LCG is below the threshold. In a case that at least one delay budget is below the threshold, the method triggers a delay information reporting (DR); determines whether at least one uplink resource is available for a MAC CE for the DR; and in a case that the at least one UL resource is available, generates the MAC CE by including delay information associated with a first delay range for the first LCG, and transmits the MAC CE on the at least one UL resource.

Abstract: Methods and devices for discontinuous reception (DRX) configurations are provided. The method includes receiving a DRX configuration via radio resource control (RRC) signaling, the DRX configuration including a first configuration for configuring a DRX cycle by an integer value; determining whether the DRX configuration includes a second configuration for configuring the DRX cycle by a non-integer value; and in a case that the DRX configuration includes the second configuration, applying the second configuration instead of the first configuration for configuring the DRX cycle.

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.