Patents by Inventor Hung-Wen Huang

Hung-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200198146
    Abstract: A calibration system for robot tool including a robot arm adopting a first coordinate system, a tool arranged on a flange of the robot arm, and an imaging device adopting a second coordinate system is disclosed, wherein an image sensing area is established by the image device. A calibration method is also disclosed and includes steps of: controlling the robot arm to move for leading a tool working point (TWP) of the tool enters the image sensing area; recording a current gesture of the robot arm as well as a specific coordinate of the TWP currently in the second coordinate system; obtaining a transformation matrix previously established for describing a relationship between the first and the second coordinate systems; and importing the specific coordinate and the current gesture to the transformation matrix for calculating an absolute position of the TWP in the first coordinate system.
    Type: Application
    Filed: March 5, 2020
    Publication date: June 25, 2020
    Inventors: Yi-Jiun SHEN, Yu-Ru HUANG, Hung-Wen CHEN
  • Publication number: 20200193635
    Abstract: An image positioning system based on upsampling and a method thereof are provided. The image positioning method based on upsampling is to fetch a region image covering a target from a wide region image, determine a rough position of the target, execute an upsampling process on the region image based on neural network data model for obtaining a super-resolution region image, map the rough position onto the super-resolution region image, and analyze the super-resolution region image for determining a precise position of the target. The present disclosed example can significantly improve the efficiency of positioning and effectively reduce the required cost of hardware.
    Type: Application
    Filed: December 14, 2019
    Publication date: June 18, 2020
    Inventors: Yu-Cheng SU, Qi-Ming HUANG, Yi-Jiun SHEN, Hung-Wen CHEN
  • Patent number: 10664117
    Abstract: A touch panel includes a base layer having a shaded area and a visible area; a first sensing layer having first capacitive sensing columns (FCSCs) and first electromagnetic antenna columns (FEACs), which are insulated; a first auxiliary conductive layer having a circuit pattern substantially identical to the first sensing layer, and the circuit pattern correspondingly electrically connecting to the first sensing layer; a second sensing layer having second capacitive sensing columns (SCSCs) and second electromagnetic antenna columns (SEACs), which are insulated; a second auxiliary conductive layer having a circuit pattern substantially identical to the second sensing layer, and the circuit pattern correspondingly connect to the second sensing layer; and an insulative layer between the first and second sensing layer.
    Type: Grant
    Filed: March 24, 2019
    Date of Patent: May 26, 2020
    Assignee: YOUNG FAST OPTOELECTRONICS CO., LTD.
    Inventors: Chih-Chiang Pai, Meng-Kuei Lin, Hung-Chi Huang, Chiu-Wen Chen
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10609472
    Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 31, 2020
    Assignee: Qisda Corporation
    Inventors: Hung-Yen Huang, Huai-Wen Hsu, Chun-Ming Shen, Chin-Kuei Lee, Cheng-Chih Huang
  • Publication number: 20200098740
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 26, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Li-Fan CHEN, Chih-Hsuan LIN, Yu-Kai WANG, Hung-Wei CHEN, Ching-Wen WANG, Ting-You LIN, Chun-Chih CHEN
  • Publication number: 20200065965
    Abstract: A computer aided method for analyzing fibrosis is provided. First, a segmentation algorithm is performed on a medical image to obtain a segmentation image. Circular fibrosis is detected according to the segmentation image to determine a score. In some cases, it is also necessary to determine a number of fibrosis bridges and the condition of fiber expansion.
    Type: Application
    Filed: August 26, 2019
    Publication date: February 27, 2020
    Inventors: Pau-Choo CHUNG CHAN, Nan-Haw CHOW, Hung-Wen TSAI, Kuo-Sheng CHENG, Chun-Cheng HUANG
  • Publication number: 20200058435
    Abstract: An inductor structure with height limit, which comprises: a conductor formed in a bent shape, and is set with a plurality of bending-portions, wherein a first connecting-pin and a second connecting-pin are respectively set at two ends of the conductor; a first magnetic core set with a first combining-surface, wherein the first combining-surface forms a concave groove to accommodate the conductor; and a second magnetic core set with a second combining-surface, wherein the second combining-surface forms a second concave groove to accommodate the conductor; wherein the second combining-surface is combined on the first combining-surface; wherein the conductor is sheathed and set between the first magnetic core and the second magnetic core, and is set with the first connecting-pin and the second connecting-pin exposedly. Therefore, the present invention can increase the magnetic (coupling) route length under the height limit to produce an effect of increasing the inductance value and current.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Chien-Chin Chang, Yu-Ting Hsu, Hung-Chih Liang, Shih-Kai Huang, Yen-Chun Wu
  • Patent number: 10554119
    Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: February 4, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chao-Li Kao, Hung-Chieh Lin, Yi-Ping Hsieh, Jin-Zhong Huang, Chao-Lung Kuo, Po-Hsin Tseng, Hong-Wen Chen
  • Publication number: 20200021182
    Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.
    Type: Application
    Filed: January 3, 2019
    Publication date: January 16, 2020
    Inventors: Chao-Li KAO, Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Chao-Lung KUO, Po-Hsin TSENG, Hong-Wen CHEN
  • Patent number: 10522281
    Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 31, 2019
    Assignee: MAG. LAYERS SCIENTIFIC-TECHNICS CO., LTD.
    Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Shih-Kai Huang, Chien-Chin Chang, Hung-Chih Liang, Yu-Ting Hsu
  • Patent number: 10509883
    Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
  • Publication number: 20190371916
    Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 5, 2019
    Inventors: Jing-Yi Lin, Yi-Wen Chen, Hung-Yi Wu, Ping-Wei Huang, Shao-Wei Wang, Yueh-Chi Chuang, Hung-Jen Huang, Hao-Che Feng
  • Publication number: 20190291217
    Abstract: A soldering process method includes the following steps. A temperature profile of generating a solder structure is measured. A final product of the solder structure is tested and recorded. A machine learning method is used to repeatedly compare and analyze a relationship between a plurality of the temperature profiles of the solder structure and a corresponding final product of the solder structure so as to find an optimal temperature profile model in accordance with quality control requirements.
    Type: Application
    Filed: August 21, 2018
    Publication date: September 26, 2019
    Inventors: Shu-Han WU, Hung-Wen CHEN, Qi-Ming HUANG, Yang-Hao CHOU, Yun-Chung SUN
  • Publication number: 20190287708
    Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Hsiu-Fa Yeh, Pin-Yu Chen, Hang-Chun Lu, Ya-Wen Yang, Shih-Kai Huang, Chien-Chin Chang, Hung-Chih Liang, Yu-Ting Hsu
  • Publication number: 20190273023
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yip LOH, Chih-Wei CHANG, Hong-Mao LEE, Chun-Hsien HUANG, Yu-Ming HUANG, Yan-Ming TSAI, Yu-Shiuan WANG, Hung-Hsu CHEN, Yu-Kai CHEN, Yu-Wen CHENG
  • Publication number: 20190182582
    Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 13, 2019
    Inventors: Hung-Yen Huang, Huai-Wen Hsu, Chun-Ming Shen, Chin-Kuei Lee, Cheng-Chih Huang
  • Publication number: 20190174661
    Abstract: An electronic-component assembly system is provided in the invention. The electronic-component assembly system includes a gripping device, a light-source device, a photographing device, and an image-processing device. The gripping device grips an electronic component, wherein the electronic component includes at least one pin. The light-source device includes a light source and emits light of the light source. The photographing device senses the light and generates a plurality of first one-dimensional images corresponding to the pins at different rotation angles. The image-processing device is coupled to the photographing device to receive the plurality of first one-dimensional images.
    Type: Application
    Filed: June 5, 2018
    Publication date: June 6, 2019
    Inventors: Yu-Ru HUANG, Hung-Wen CHEN
  • Publication number: 20190172949
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20190157141
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 23, 2019
    Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU