Patents by Inventor Hung-Wen Huang
Hung-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11260508Abstract: A torque socket tool is provided, including: a main body, a driving member, an engaging member, a torque adjustment assembly and a rotating member. The main body defines an axial direction and has a first restricting portion. The driving member is rotatably disposed on the main body about the axial direction. The engaging member is slidably disposed on the main body. The torque adjustment assembly includes a mandrel. The mandrel is disposed within the main body and rotatable about the axial direction. The rotating member is non-rotatably sleeved with the mandrel and has a second restricting portion.Type: GrantFiled: September 30, 2020Date of Patent: March 1, 2022Inventor: Hung-Wen Huang
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Patent number: 11207764Abstract: A torque socket tool includes a main body, a driving portion, an abutting member, an axle, and a sleeve member. The main body defines an axial direction. The abutting member is non-rotatably and slidably arranged in the main body. The sleeve member is rotatably sleeved onto the main body. A threaded section drives the abutting member to slide along the axial direction for adjusting the predetermined torque when the axle is rotated by rotating the sleeve member.Type: GrantFiled: January 10, 2020Date of Patent: December 28, 2021Inventor: Hung-Wen Huang
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Patent number: 11203100Abstract: A torque structure includes a first body provided with a receiving recess, a second body pivotally connected with the first body, a first elastic member received in the second body, a retaining unit including a mounting seat provided with a first threaded portion and a plurality of first through holes, a first adjusting member provided with a head, a positioning seat provided with a plurality of second through holes, and a locking unit including a plurality of first locking members, a second locking member, a plurality of third locking members, a fourth locking member, a fastening member, and a second adjusting member. The fastening member is provided with a fitting portion connected with the first body. The fastening member is provided with a third threaded portion. The second adjusting member is provided with a fourth threaded portion screwed into the third threaded portion.Type: GrantFiled: January 15, 2020Date of Patent: December 21, 2021Inventors: Wen-Chin Kuo, Hung-Wen Huang
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Publication number: 20210379742Abstract: A torque wrench is provided, including a main body, a driving portion, a positioning member, a torque adjusting assembly and a tripping assembly. The main body defines an axial direction. The driving portion is disposed on an end of the main body. The positioning member is fixedly disposed in the main body. The torque adjusting assembly includes an abutting member and a mandrel, and the mandrel is disposed in the main body, rotatable about the axial direction and screwed to the abutting member. The tripping assembly includes an elastic abutting member and a plurality of notches arranged circumferentially one of the elastic abutting member and the plurality of notches is disposed on the mandrel, and the other of the elastic abutting member and the plurality of notches is disposed on the positioning member.Type: ApplicationFiled: April 20, 2021Publication date: December 9, 2021Inventor: HUNG-WEN HUANG
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Publication number: 20210213592Abstract: A torque structure includes a first body provided with a receiving recess, a second body pivotally connected with the first body, a first elastic member received in the second body, a retaining unit including a mounting seat provided with a first threaded portion and a plurality of first through holes, a first adjusting member provided with a head, a positioning seat provided with a plurality of second through holes, and a locking unit including a plurality of first locking members, a second locking member, a plurality of third locking members, a fourth locking member, a fastening member, and a second adjusting member. The fastening member is provided with a fitting portion connected with the first body. The fastening member is provided with a third threaded portion. The second adjusting member is provided with a fourth threaded portion screwed into the third threaded portion.Type: ApplicationFiled: January 15, 2020Publication date: July 15, 2021Inventors: Wen-Chin Kuo, Hung-Wen Huang
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Publication number: 20210187712Abstract: A torque socket tool is provided, including: a main body, a driving member, an engaging member, a torque adjustment assembly and a rotating member. The main body defines an axial direction and has a first restricting portion. The driving member is rotatably disposed on the main body about the axial direction. The engaging member is slidably disposed on the main body. The torque adjustment assembly includes a mandrel. The mandrel is disposed within the main body and rotatable about the axial direction. The rotating member is non-rotatably sleeved with the mandrel and has a second restricting portion.Type: ApplicationFiled: September 30, 2020Publication date: June 24, 2021Inventor: HUNG-WEN HUANG
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Publication number: 20200298383Abstract: A torque socket tool includes a main body, a driving portion, an abutting member, an axle, and a sleeve member. The main body defines an axial direction. The abutting member is non-rotatably and slidably arranged in the main body. The sleeve member is rotatably sleeved onto the main body. A threaded section drives the abutting member to slide along the axial direction for adjusting the predetermined torque when the axle is rotated by rotating the sleeve member.Type: ApplicationFiled: January 10, 2020Publication date: September 24, 2020Inventor: HUNG-WEN HUANG
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Patent number: 10629734Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: GrantFiled: January 18, 2019Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Patent number: 10509883Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: GrantFiled: January 24, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Yu Yang, Wei-Yi Hu, Jui-Feng Kuan, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang, Hung-Ming Chen, Abhishek Patyal
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Publication number: 20190172949Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: ApplicationFiled: January 18, 2019Publication date: June 6, 2019Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Patent number: 10229995Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: GrantFiled: August 4, 2017Date of Patent: March 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Publication number: 20190027602Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.Type: ApplicationFiled: August 4, 2017Publication date: January 24, 2019Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Publication number: 20180358453Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.Type: ApplicationFiled: July 6, 2017Publication date: December 13, 2018Inventors: Hung-Wen Huang, Kai-Lin Lee, Ren-Yu He, Chi-Hsiao Chen, Ting-Hsuan Kang, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
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Publication number: 20180150585Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.Type: ApplicationFiled: January 24, 2017Publication date: May 31, 2018Inventors: Tsun-Yu YANG, Wei-Yi HU, Jui-Feng KUAN, Hsien-Hsin Sean LEE, Po-Cheng PAN, Hung-Wen HUANG, Hung-Ming CHEN, Abhishek PATYAL
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Patent number: 9800462Abstract: A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.Type: GrantFiled: November 2, 2015Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Yun-Ting Hsu, Tsungwu Yu, Yu Yu, Hung-Wen Huang
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Patent number: 9473352Abstract: A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.Type: GrantFiled: July 29, 2014Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Yun-Ting Hsu, Tsungwu Yu, Yu Yu, Hung-Wen Huang
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Publication number: 20160247973Abstract: A Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Hung-Wen HUANG, Hsing-Kuo HSIA, Ching-Hua CHIU
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Publication number: 20160057007Abstract: A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.Type: ApplicationFiled: November 2, 2015Publication date: February 25, 2016Inventors: YUN-TING HSU, TSUNGWU YU, YU YU, HUNG-WEN HUANG
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Publication number: 20160035933Abstract: A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Yea-Chen LEE, Jung-Tang CHU, Ching-Hua CHIU, Hung-Wen HUANG
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Patent number: D820261Type: GrantFiled: April 3, 2017Date of Patent: June 12, 2018Assignee: Logitech Europe S.A.Inventors: Bengt Brummer, Hung-Wen Huang, Jasper Phua, Olivier Dumont, Sylvain Sauvage