Abstract: A calibration system for robot tool including a robot arm adopting a first coordinate system, a tool arranged on a flange of the robot arm, and an imaging device adopting a second coordinate system is disclosed, wherein an image sensing area is established by the image device. A calibration method is also disclosed and includes steps of: controlling the robot arm to move for leading a tool working point (TWP) of the tool enters the image sensing area; recording a current gesture of the robot arm as well as a specific coordinate of the TWP currently in the second coordinate system; obtaining a transformation matrix previously established for describing a relationship between the first and the second coordinate systems; and importing the specific coordinate and the current gesture to the transformation matrix for calculating an absolute position of the TWP in the first coordinate system.

Abstract: An image positioning system based on upsampling and a method thereof are provided. The image positioning method based on upsampling is to fetch a region image covering a target from a wide region image, determine a rough position of the target, execute an upsampling process on the region image based on neural network data model for obtaining a super-resolution region image, map the rough position onto the super-resolution region image, and analyze the super-resolution region image for determining a precise position of the target. The present disclosed example can significantly improve the efficiency of positioning and effectively reduce the required cost of hardware.

Abstract: A touch panel includes a base layer having a shaded area and a visible area; a first sensing layer having first capacitive sensing columns (FCSCs) and first electromagnetic antenna columns (FEACs), which are insulated; a first auxiliary conductive layer having a circuit pattern substantially identical to the first sensing layer, and the circuit pattern correspondingly electrically connecting to the first sensing layer; a second sensing layer having second capacitive sensing columns (SCSCs) and second electromagnetic antenna columns (SEACs), which are insulated; a second auxiliary conductive layer having a circuit pattern substantially identical to the second sensing layer, and the circuit pattern correspondingly connect to the second sensing layer; and an insulative layer between the first and second sensing layer.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.

Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.

Abstract: A computer aided method for analyzing fibrosis is provided. First, a segmentation algorithm is performed on a medical image to obtain a segmentation image. Circular fibrosis is detected according to the segmentation image to determine a score. In some cases, it is also necessary to determine a number of fibrosis bridges and the condition of fiber expansion.

Abstract: An inductor structure with height limit, which comprises: a conductor formed in a bent shape, and is set with a plurality of bending-portions, wherein a first connecting-pin and a second connecting-pin are respectively set at two ends of the conductor; a first magnetic core set with a first combining-surface, wherein the first combining-surface forms a concave groove to accommodate the conductor; and a second magnetic core set with a second combining-surface, wherein the second combining-surface forms a second concave groove to accommodate the conductor; wherein the second combining-surface is combined on the first combining-surface; wherein the conductor is sheathed and set between the first magnetic core and the second magnetic core, and is set with the first connecting-pin and the second connecting-pin exposedly. Therefore, the present invention can increase the magnetic (coupling) route length under the height limit to produce an effect of increasing the inductance value and current.

Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.

Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.

Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.

Abstract: A soldering process method includes the following steps. A temperature profile of generating a solder structure is measured. A final product of the solder structure is tested and recorded. A machine learning method is used to repeatedly compare and analyze a relationship between a plurality of the temperature profiles of the solder structure and a corresponding final product of the solder structure so as to find an optimal temperature profile model in accordance with quality control requirements.

Abstract: The large-current inductor includes a first core member having a first winding piece, a second winding piece, a first indentation, and a second indentation; a second core member having a third winding piece, a fourth winding piece, a third indentation, and a fourth indentation; a third core member attached and joined to first lateral sides of the first and second core members; and a fourth core member attached and joined to second lateral sides of the first and second core members. A first coil member winds around the first and third winding pieces, and has its ends embedded into the first and third indentations. A second coil member winds around the second and fourth winding pieces, and has its ends embedded into the second and fourth indentations. The inductor enhances efficiency of energy storage by mutual inductance, and limits large current flow by leakage inductance.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: A speaker module includes a bracket, a plurality of first cushion members, a speaker and a plurality of second cushion members. The bracket includes a plurality of first pillars. Each of the first cushion members is disposed on one of the first pillars. The speaker is connected to the first cushion members. The second cushion members are connected to a periphery of the bracket.

Abstract: An electronic-component assembly system is provided in the invention. The electronic-component assembly system includes a gripping device, a light-source device, a photographing device, and an image-processing device. The gripping device grips an electronic component, wherein the electronic component includes at least one pin. The light-source device includes a light source and emits light of the light source. The photographing device senses the light and generates a plurality of first one-dimensional images corresponding to the pins at different rotation angles. The image-processing device is coupled to the photographing device to receive the plurality of first one-dimensional images.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.