Patents by Inventor Hung-Yi Lin

Hung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230280558
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: May 5, 2023
    Publication date: September 7, 2023
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20230282144
    Abstract: An arcuate display device includes a plurality of display units each having has a plurality of pixels, a virtual axis, and a plurality of driving devices. Each pixel includes first, second, and third light-emitting elements respectively disposed at first, second, and third positions. The driving devices corresponding to the display units having the same minimum distance from the virtual axis have the same circuit layout design. The first, second, and third positions are sequentially arranged in a direction away from the virtual axis. Optical properties of the first light-emitting elements and the third light-emitting elements in at least a part of the pixels disposed at a first side of the virtual axis are respectively substantially the same as optical properties of the third light-emitting elements and the first light-emitting elements in at least a part of the pixels disposed at a second side of the virtual axis.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Applicant: AUO Corporation
    Inventors: Kai-Yi Lu, Hung-Chi Wang, Chen-Yu Lin, Ya-Fang Chen, Chih-Hsiang Yang
  • Publication number: 20230275030
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 31, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20230267086
    Abstract: A serial peripheral interface circuit includes a serial peripheral interface device with a master-in-slave-out (MISO) line, a master-out-slave-in (MOSI) line, a serial clock (SCLK) line and a slave select (SS) line, a first conducting line, a second conducting line, a first resistor connecting the MISO line and the first conducting line, and a second resistor connecting the MOSI line and the second conducting line.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Inventors: Hung-Yi LAI, Cheng-Hung HO, Hsin-Wen LIN
  • Publication number: 20230268426
    Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 24, 2023
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230270017
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.
    Type: Application
    Filed: March 24, 2022
    Publication date: August 24, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Yi Wu, Jia-Rong Wu, Yu-Hsiang Lin, Yi-Wen Chen, Kun-Sheng Yang
  • Publication number: 20230245967
    Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20230236372
    Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
  • Publication number: 20230221772
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 13, 2023
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Publication number: 20230215822
    Abstract: An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Wei HSIEH, Hung-Yi LIN, Hsu-Chiang SHIH, Cheng-Yuan KUNG
  • Publication number: 20230215816
    Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hsu-Chiang SHIH, Hung-Yi LIN, Chien-Mei HUANG
  • Publication number: 20230205072
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
  • Patent number: 11686908
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20230199362
    Abstract: The present disclosure provides a wearable component. The wearable component includes a first carrier and a first electronic component at least partially embedded within the first carrier. The first carrier and the first electronic component define a space configured for audio transmission. An ear tip and a method of manufacturing a wearable component are also provided.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Yi WU, Hung Yi LIN, Jenchun CHEN
  • Patent number: 11664325
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20230098532
    Abstract: An electronic device includes: at least one connection interface, to receive an external signal. A first signal switching multiplexer is connected to the connection interface. A laptop system is connected to the first signal switching multiplexer, to operate in a laptop mode. A drawing board system is connected to the first signal switching multiplexer, to operate in a drawing board mode and an independent screen mode. A switching switch generates a switching signal and transmits it to the first signal switching multiplexer, the laptop system, and the drawing board system, to select the laptop mode, the drawing board mode, or the independent screen mode.
    Type: Application
    Filed: August 24, 2022
    Publication date: March 30, 2023
    Inventors: Yi-Lun Lai, Cheng-Hui Wu, Huan-Hsun Huang, Hung-Yi Lin, Yi-Ou Wang
  • Publication number: 20230078564
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
  • Publication number: 20230077877
    Abstract: A photonic package and a method of manufacturing a photonic package are provided. The photonic package includes a carrier, an electronic component, and a photonic component. The carrier has a first surface and a recess portion exposed from the first surface. The electronic component is disposed in recessed portion. The photonic component is disposed on and electrically connected to the electronic component and is configured to communicate optical signals.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20230065615
    Abstract: An electronic device includes a first electronic component, an encapsulant and a second electronic component. The encapsulant encapsulates the first electronic component. The second electronic component is disposed over the first electronic component and separated from the encapsulant. The second electronic component is configured to receive a power from the first electronic component.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen