Patents by Inventor Hung-Yi Lin

Hung-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11545427
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Chien-Hua Chen, Teck-Chong Lee, Hung-Yi Lin, Pao-Nan Lee, Hsin Hsiang Wang, Min-Tzu Hsu, Po-Hao Chen
  • Publication number: 20220384308
    Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao-Yen LEE, Hung-Yi LIN
  • Publication number: 20220384309
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chin-Cheng KUO, Wu Chou HSU
  • Patent number: 11508668
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
  • Publication number: 20220359425
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • Patent number: 11455046
    Abstract: An electronic device suitable for a stylus is provided. The electronic device includes a display panel, a touch module, and a processor. The display panel includes a display area. The touch module includes a touchable area. The processor is electrically connected to the display panel and the touch module. The processor defines an effective input area in the touchable area in response to the operation of the stylus, defines a mapping display area in the display area corresponding to the effective input area, and adjusts the display ratio of the mapping display area according to the input ratio of the effective input area.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 27, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Ya-Ting Chen, Hung-Yi Lin, Chien-Chih Tseng, Chun-Tsai Yeh, Wei-Tong Lin, Ming-Chieh Chen, Yi-Ou Wang, Chao-Chieh Cheng
  • Publication number: 20220293538
    Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.
    Type: Application
    Filed: May 31, 2022
    Publication date: September 15, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 11435844
    Abstract: An electronic device and its force touch assembly are provided. The force touch assembly includes a first substrate, a second substrate, a first patterned conductive layer, an insulation layer, a second patterned conductive layer, a plurality of variable pressure sensitive materials and a third patterned conductive layer, wherein the first patterned conductive layer, the insulation layer, the second patterned conductive layer, the plurality of variable pressure sensitive materials and the third patterned conductive layer are sequentially stacked from top to bottom between the first substrate and the second substrate.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 6, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Ching-Fu Hsu, Wei-Ting Wong, Chun-Wei Li, Hung-Yi Lin
  • Patent number: 11410594
    Abstract: A method of dynamic bias control of a source driver bases on data wing level for power-saving. In order to cover the operating conditions of various loads under normal operations, the output buffer circuit operation is biased. The method utilizes the display gray scale difference between a previous data line and an immediately subsequent data line to determine the bias current to be used for the output buffer. When the difference between the current data line display gray scale and the previous data line display gray scale is not large, the bias current of the output buffer can be reduced. When the difference between the current data line display gray scale and the previous data line display gray scale is large, the bias current of the output buffer is increased and the current of the output buffer is adjusted according to different load conditions to save power.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 9, 2022
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Chia-Hsin Tung, Hsin-Hung Ou, Hung-Yi Lin
  • Patent number: 11402992
    Abstract: A control method applied to an electronic device with a first screen and a second screen is provided. The control method includes the following steps: receiving touch data responding to a touch behavior generated by the second screen; determining whether the touch behavior is a touchpad operation instruction or a touch screen operation instruction according to the touch data; triggering corresponding touchpad operation according to the touch data when the touch behavior is the touchpad operation instruction; and triggering corresponding touch screen operation according to the touch data when the touch behavior is the touch screen operation instruction.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 2, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Tsai Yeh, Hung-Yi Lin, Meng-Ju Lu, Chien-Chih Tseng
  • Publication number: 20220181268
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Meng-Wei HSIEH, Yu-Pin TSAI
  • Patent number: 11348885
    Abstract: A semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 31, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin
  • Patent number: 11342282
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Chiang Shih, Hung-Yi Lin, Meng-Wei Hsieh, Yu Sheng Chang, Hsiu-Chi Liu, Mark Gerber
  • Publication number: 20220157709
    Abstract: A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar.
    Type: Application
    Filed: November 18, 2020
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang Shih, Meng-Wei Hsieh, Hung-Yi Lin, Cheng-Yuan Kung
  • Publication number: 20220148974
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 11302267
    Abstract: A driving device and an operation method thereof are provided. The driver device includes a source driver circuit, an output switching circuit, and an equalization control circuit. Two input ends of the output switching circuit are coupled to two output ends of the source driver circuit. Two output ends of the output switching circuit are coupled to two data lines of an LED display panel. The equalization control circuit checks whether sub-pixel data of the two data lines meets a predetermined condition. A plurality of sub-pixels located on a current display line of the LED display panel are reset in a reset period. In a data scanning period after the reset period, the equalization control circuit determines whether to control the output switching circuit to perform an equalization operation on the two data lines according to the checking result.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: April 12, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Hung Chen, Chia-Hsin Tung, Hsin-Hung Ou, Hung-Yi Lin
  • Patent number: 11296043
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chang-Yu Lin
  • Patent number: 11233010
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 25, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin
  • Patent number: 11201125
    Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Chi Hsieh, Hung-Yi Lin, Cheng-Yuan Kung, Pao-Nan Lee, Chien-Hua Chen
  • Patent number: 11189604
    Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chao-Kai Hung, Chien-Wei Chang, Ya-Chen Shih, Hung-Jung Tu, Hung-Yi Lin, Cheng-Yuan Kung