Patents by Inventor Hung Yi

Hung Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONDUCTIVE STRUCTURE INTERCONNECTS
    Publication number: 20230395504
    Abstract: Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu Pei Chen, Chia-Hao Chang, Shin-Yi Yang, Chia-Hung Chu, Po-Chin Chang, Shuen-Shin Liang, Chun-Hung Liao, Yuting Cheng, Hung-Yi Huang, Harry Chien, Pinyen Lin, Sung-Li Wang
  • CONDUCTIVE STRUCTURES AND METHODS OF FORMING THE SAME
    Publication number: 20230395429
    Abstract: Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventors: Kan-Ju LIN, Hao-Heng LIU, Chien CHANG, Hung-Yi HUANG, Harry CHIEN
  • Packaged semiconductor devices with wireless charging means
    Patent number: 11837517
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a semiconductor device, a molding material surrounding the semiconductor device, and a conductive slot positioned over the molding material. The conductive slot has an opening and at least two channels connecting the opening to the edges of the conductive slot, and at least two of the channels extend in different directions.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Tzu-Sung Huang, Ming-Hung Tseng, Hung-Yi Kuo
  • DUAL-MODE WIRELESS CHARGING DEVICE
    Publication number: 20230387003
    Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei LIANG, Hung-Yi KUO, Hao-Yi TSAI, Ming-Hung TSENG, Hsien-Ming TU
  • METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING
    Publication number: 20230384537
    Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Hao CHEN, Chung-Ming WENG, Tsung-Yuan YU, Hui Yu LEE, Hung-Yi KUO, Jui-Feng KUAN, Chien-Te WU
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230378026
    Abstract: A semiconductor package and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a substrate and transistors formed at a front side of the substrate; a power distribution network, spreading at a back side of the substrate and penetrating through the substrate, to provide power and ground signals to the transistors; a dielectric material, laterally surrounding the first semiconductor die; and a second semiconductor die, having a central portion bonded with the first semiconductor die and a peripheral portion in contact with the dielectric material.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Cheng-Chieh Hsieh, Kuo-Chung Yee, Chen-Hua Yu
  • Heater package
    Patent number: 11825570
    Abstract: An embodiment of the disclosure provides a heater package including a substrate, a first barrier layer, at least one heater, and a second barrier layer. The first barrier layer is disposed on a surface of the substrate and has a first treatment layer on a side away from the substrate. The heater is disposed on the substrate and includes a heating layer and at least one electrode. The at least one electrode and the heating layer contact with each other. The second barrier layer covers an upper surface and a sidewall of the heater and has a second treatment layer on an opposite side or the side away from the substrate. A ratio of a thickness of the first treatment layer to a thickness of the first barrier layer and a ratio of a thickness of the second treatment layer to a thickness of the second barrier layer range from 0.03 to 0.2.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 21, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Ching Kuo, Chien-Chang Hung, Hong-Ming Dai, Jane-Hway Liao, Hung-Yi Chen, Shu-Tang Yeh
  • Semiconductor package structure
    Patent number: 11824029
    Abstract: A semiconductor package structure includes a first semiconductor die having an active surface and a passive surface opposite to the active surface, a conductive element leveled with the first semiconductor die, a first redistribution layer (RDL) being closer to the passive surface than to the active surface, a second RDL being closer to the active surface than to the passive surface, and a second semiconductor die over the second RDL and electrically coupled to the first semiconductor die through the second RDL. A first conductive path is established among the first RDL, the conductive element, the second RDL, and the active surface of the first semiconductor die.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Han Chen, Hung-Yi Lin
  • PROGRAMMABLE INDUCTOR AND METHODS OF MANUFACTURE
    Publication number: 20230368972
    Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Nien-Fang Wu
  • SEMICONDUCTOR PACKAGE
    Publication number: 20230367062
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Interconnect structure and manufacturing method for the same
    Patent number: 11817384
    Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
  • BACKLIGHT MODULE AND DISPLAY DEVICE
    Publication number: 20230360611
    Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes a light source structure and an optical film. The light source structure includes a substrate, plural light-emitting units and a package structure. The light-emitting units are disposed on the substrate. The package structure covers the light-emitting units, and the package structure has plural convex portions. The optical film is disposed on the light source structure, and the optical film is in contact with the convex portions of the package structure.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Jui-Lin CHEN, Pin-Hsun LEE, Yuan-Jhang CHEN, Che-Kai CHANG, Chun-Hung HO, Hung-Yi CHEN
  • Photonic integrated circuit and package structure
    Patent number: 11809000
    Abstract: A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Ming Weng, Hua-Kuei Lin, Che-Hsiang Hsu
  • METHODS AND SYSTEMS FOR IMPROVING PLASMA IGNITION STABILITY
    Publication number: 20230352309
    Abstract: Methods for plasma stability in a plasma treatment tool are disclosed. A laser is positioned within a plasma treatment chamber within a skin depth of the electromagnetic field generated therein. The laser can be synchronized with the electrical triggering signals that generate the electromagnetic field. This scheme provides a stable and efficient method of plasma ignition.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Ping-Hsun Lin, Hung-Yi Tsai, Hao-Ping Cheng, Ta-Cheng Lien, Hsin-Chang Lee
  • EUV PHOTO MASKS AND MANUFACTURING METHOD THEREOF
    Publication number: 20230350283
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.
    Type: Application
    Filed: June 26, 2023
    Publication date: November 2, 2023
    Inventors: Pei-Cheng HSU, Ching-Huang CHEN, Hung-Yi TSAI, Ming-Wei CHEN, Hsin-Chang LEE, Ta-Cheng LIEN
  • Assembly structure and package structure
    Patent number: 11798890
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin
  • ELECTRONIC PACKAGE
    Publication number: 20230326861
    Abstract: An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Yi LIN, Cheng-Yuan KUNG
  • ELECTRONIC PACKAGE
    Publication number: 20230326889
    Abstract: An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Yi Lin, Cheng-Yuan Kung
  • Semiconductor device and method for manufacturing the same
    Patent number: 11784111
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Wu Chou Hsu
  • Optical interconnect structure, package structure and fabricating method thereof
    Patent number: 11768338
    Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Yu-Hsiang Hu, Chewn-Pu Jou, Feng-Wei Kuo