Abstract: Some embodiments of the present disclosure provide a semiconductor device including a contact electrically connected to an III-V semiconductor bulk layer. A metal layer stack of the contact includes metal layers and a metal nitride capping layer at the topmost layer of the metal layer stack. The metal layers include a metal bottom layer having a metal element at the bottommost layer of the metal layer stack, where the metal nitride capping layer has a nitride of the metal element. A thickness of the metal bottom layer is larger than a thickness of the metal nitride capping layer.

Abstract: A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.

Abstract: A suspension ball joint includes a base cap, an interior of which accommodates a bearing socket, a ball stud, a restriction unit disposed on a top of the bearing socket, and an elastic unit disposed on a top of the restriction unit. A cover unit is disposed on a top of the elastic unit. The bearing socket is made of metal and tightly engaged with the base cap, thereby increasing the strength and preventing the bearing socket from rubbing against the base cap while operating the ball stud. When the restriction unit, the elastic unit, and the cover unit are sequentially arranged within the interior of the base cap, the concatenation of these units prevents improper pressing forces, thereby preventing the ball stud from rubbing against the bearing socket. Thus, the service life and the durability of the suspension ball joint are improved.

Abstract: A range hood is disclosed and includes a guiding cover, a guiding duct, an air guiding fan, an electrostatic oil fume separator and a networked controller. The guiding cover is arranged in a kitchen space, two deflectors are extended from two sides of the guiding cover for blocking air pollution from spreading and concentrating to an air guiding path. The guiding duct communicates to the air guiding path. The air guiding fan communicates to the guiding duct. The electrostatic oil fume separator is arranged above the guiding cover to separate oil droplets and smoke gas. The networked controller receives a control command of an indoor air pollution prevention system through a networked communication, so as to control an activation operation of the air guiding fan, thereby the air pollution of the kitchen space can be detected in real time and purified to a level close to zero.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip structure over a substrate. The method includes forming an adhesive wall structure over the substrate and surrounding the chip structure. The adhesive wall structure has a convex curved sidewall facing away from the chip structure. The method includes forming an adhesive layer over the substrate. The adhesive layer surrounds the adhesive wall structure, and a first Young's modulus of the adhesive layer is different from a second Young's modulus of the adhesive wall structure. The method includes disposing a heat-spreading lid over the adhesive layer to cover the adhesive wall structure and the chip structure. The heat-spreading lid is bonded to the adhesive layer and the adhesive wall structure.

Abstract: A semiconductor structure includes a gate structure on a semiconductor layer on a substrate, a first dielectric layer continuously extending on the gate structure and the semiconductor layer and including a third portion on an upper surface of the gate structure, a first portion and a second portion closer to the third portion than the first portion, a second dielectric layer on an etch stop layer on at least the first portion, and a field-plate. The field-plate includes a first field-plate portion on the second dielectric layer and a second field-plate portion and a third field-plate portion on the second portion and the third portion. A lower surface of the first field-plate portion is farther away from the semiconductor layer compared to a lower surface of the second field-plate portion. On the substrate, a projection of the field-plate completely covers a projection of the gate structure.

Abstract: A semiconductor structure includes a gate structure on a semiconductor layer on a substrate, a first dielectric layer continuously extending on the gate structure and the semiconductor layer and including a first portion and a second portion, a second dielectric layer on an etch stop layer on at least the first portion of the first dielectric layer, and a field plate including a first field-plate portion on the second dielectric layer and a second field-plate portion on the second portion of the first dielectric layer. Lower surfaces of the first field-plate portion and the second field-plate portion are respectively distanced from the semiconductor layer with a first distance and a second distance that is smaller than the second distance. The field plate and the gate structure respectively have a first projection and a second projection that is not overlapped with the first projection on the substrate.

Abstract: A semiconductor structure includes a gate structure on a semiconductor layer on a substrate; a first dielectric layer continuously extending on the gate structure and the semiconductor layer and including a third portion and a fourth portion on an upper surface of the gate structure, a first portion, and a second portion; a second dielectric layer on an etch stop layer on at least the first portion and the fourth portion; and a field-plate. The field-plate includes a first field-plate portion and a fourth field-plate portion on the second dielectric layer and includes a second field-plate portion and a third field-plate portion on the second portion and the fourth portion, respectively. Lower surfaces of the first field-plate portion and the fourth field-plate portion are farther away from the semiconductor layer compared to lower surfaces of the second field-plate portion and the third field-plate portion, respectively.

Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.

Abstract: An embodiment is a device including a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a first side of the package component. The device also includes a metal layer on a second side of the package component, the second side being opposite the first side. The device also includes a thermal interface material on the metal layer. The device also includes a lid on the thermal interface material. The device also includes a retaining structure on sidewalls of the package component and the thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.

Abstract: A method of forming a semiconductor device includes forming a channel layer and a barrier layer on a substrate; forming a gate structure on the barrier layer, conformally forming a first dielectric layer on the barrier layer and the gate structure; forming a second dielectric layer spaced apart from the gate structure on the first dielectric layer; forming an ohmic contact metal layer on the first dielectric layer and the second dielectric layer, in which the ohmic contact metal layer contacts the barrier layer through a first opening and a second opening of the first dielectric layer; and etching the ohmic contact metal layer. A source electrode filled in the first opening, a drain electrode filled in the second opening, and a field plate disposed between the source electrode and the drain electrode and partially covering the second dielectric layer are formed. A semiconductor device is also disclosed.

Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.

Abstract: A method for manufacturing a nitrile butadiene rubber includes: subjecting a material composition containing water, butadiene, acrylonitrile, an emulsifying agent, an initiator, and a molecular weight regulator to an emulsion polymerization reaction, so as to form an emulsion; and adding a reactive antioxidant and a non-reactive antioxidant to the emulsion to form a mixture, followed by subjecting the mixture to a coagulation process, so as to form the nitrile butadiene rubber.

Abstract: A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: A switch mode power supply circuit with high voltage output, an electrostatic spray apparatus and agricultural plant protection apparatus using the same are provided. The switch mode power supply circuit is electrically connected in series with at least a pre-stage power converter and a post-stage power converter. In order to simplify the control, the switch of the pre-stage power converter is omitted, only one switch of the post-stage power converter is adopted to perform synchronous control. Since the multiple sets of power conversion circuits in the previous stage are connected in series, the turn ratio of the transformer in the power converter in the subsequent stage can be reduced. Therefore, the transformer can be miniaturized and the power supply circuit would be more suitable for agricultural plant protection machine and electrostatic spray apparatus.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.