Abstract: A liquid crystal display includes an insulating substrate, a plurality of parallel gate lines disposed on the insulating substrate, and a plurality of data lines disposed on the insulating substrate. The data lines insulatingly intercross the gate lines. An intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines defines a pixel region. Each pixel region includes a first thin film transistor (TFT), a first pixel electrode, and a second pixel electrode. The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the first pixel electrode, and a first drain electrode connected with the first pixel electrode. A voltage of the first pixel electrode is different from a voltage of the second pixel electrode.

Abstract: A vertical alignment liquid crystal display device includes a number of pixel regions. Each pixel region includes a lower substrate unit and an upper substrate unit having an upper glass layer, a first protrusion and a second protrusion formed on the upper glass layer, and a conductive layer formed on the second protrusion. Each of the first and second protrusions includes two uneven sections. A first potential difference is applied between the upper glass layer and the lower substrate unit, and a second potential difference, being independent from the first potential difference, is applied between the conductive layer formed on the second protrusion and the lower substrate unit.

Abstract: An exemplary TFT array substrate includes: an insulating substrate (201), a gate line (23) and a repair structure (272) arranged on the insulating substrate, a gate insulating layer (204) covering the gate line and the repair structure; a data line (27) arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The repair structure has a gap (274). The gap of the repair structure is located at where the repair structure overlapping to the gate line.

Abstract: A hydrogenation catalyst system is provided. The catalyst system includes a metal complex of Formula (I), an organic lithium compound and an organic compound having a cyclic structure including at least one double bond. In Formula (I), M is transition metals. R1, R2, R3, R4 and R5 are the same or different, including hydrogen, C1-8 alkyl, and C1-8 alkoxy, or two of R1, R2, R3, R4 and R5 are linked together to form a ring. X1, X2 and X3 are a cyclic group, hydrogen, chlorine, bromine, alkyl or alkoxy, wherein when one of X1, X2 and X3 is a cyclic group, and the others are the same or different, including hydrogen, chlorine, bromine, alkyl or alkoxy. The invention also provides a selective hydrogenation process utilizing the catalyst system.

Abstract: An exemplary liquid crystal panel (400) includes a first substrate (401) having a common electrode layer (429), a second substrate (402) parallel to the first substrate, and a liquid crystal layer (403) between the first and second substrates. The liquid crystal layer defines an active area (406) thereat. The second substrate includes common lines (440). Electrical coupling elements are disposed at the active area, so as to electrically couple the common electrode layer to the common lines.

Abstract: An exemplary liquid crystal panel (20) includes a first substrate (22), a second substrate (24) facing toward the first substrate (22), a liquid crystal layer (23) sandwiched between the two substrates, and a plurality of the conductive adhesive blocks (225) in the non-displaying region. The first substrate includes a non-displaying region (222). A transparent conductive layer (226) is disposed at a surface of the first substrate and capable of transmitting a common voltage signal to the liquid crystal layer. The first substrate at the non-displaying region includes protrusions (253) defining a plurality of gaps (254) therebetween. The transparent conductive layer covers the protrusions including parts of the protrusions defining the gaps. The conductive adhesive blocks contact the transparent conductive layer at the non-displaying region.

Abstract: An LCD includes data lines, gate lines intersecting with the data lines, and pixel units. Each pixel unit is defined by a minimal area formed by two adjacent data lines and two adjacent gate lines. Each pixel unit includes a first sub pixel unit and a second sub pixel unit. The first sub pixel unit includes a first thin film transistor (TFT) and a first pixel electrode. The second sub pixel unit includes a second TFT and a second pixel electrode. A gate electrode of the first TFT is connected to the gate line, a source electrode of the first TFT is connected to the data line. A source electrode of the second TFT is connected to a same data line, and a gate electrode of the second TFT is electrically floating.

Abstract: An exemplary in-plane switching mode liquid crystal display (IPS-LCD) panel (100) includes a thin film transistors (TFT) substrate (120), a color filter (CF) substrate (110) facing the TFT substrate, a liquid crystal layer (130) sandwiched between the two substrates. The TFT substrate includes a plurality of gate lines and source bus lines (121, 122) defining pixel regions. Each of the pixel regions includes a pair of source bus lines, a pixel electrode (125) therebetween and parallel to the source bus lines, a pair of shield metal lines (123) located at two opposite sides of the pixel electrode, a pair of common electrodes (126) that are parallel to the pixel electrode and partly overlap the shield metal lines respectively. Each of the common electrodes includes a slit (1261) therein in order to attenuate any crosstalk between the source bus line and the pixel electrode.

Abstract: An exemplary liquid crystal display (100) includes gate lines (122), and data lines (123) cooperatively defining pixel units. Each pixel unit includes a first thin film transistor (TFT) (125), a second TFT (126), a first pixel electrode (127), and a second pixel electrode (128). Gate electrodes of the two TFTs are connected to one of the gate lines. A source electrode of the first TFT is connected to one of the data lines. A drain electrode of the first TFT is connected to the first pixel electrode. A source electrode of the second TFT is connected to the first pixel electrode. A drain electrode of the second TFT is connected to the second pixel electrode. A channel width/length ratio of the second TFT is such that a voltage of the drain electrode thereof is less than a voltage of the source electrode thereof when the second TFT is switched on.

Abstract: A liquid crystal display includes an insulating substrate, a plurality of parallel gate lines disposed on the insulating substrate, and a plurality of data lines disposed on the insulating substrate. The data lines insulatingly intercross the gate lines. An intersection between two of the plurality of gate lines and a corresponding two of the plurality of data lines defines a pixel region. Each pixel region includes a first thin film transistor (TFT), a first pixel electrode, and a second pixel electrode. The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the first pixel electrode, and a first drain electrode connected with the first pixel electrode. A voltage of the first pixel electrode is different from a voltage of the second pixel electrode.

Abstract: A liquid crystal panel (200) includes parallel gate lines (212), and parallel data lines (213) insulatingly intercrossing the gate lines. The gate lines and the data lines define a plurality of pixel regions (211). Each pixel region includes a first thin film transistor (TFT) (215), a second TFT (216), a first pixel electrode (217), and a second pixel electrode (218). The first TFT includes a first gate electrode connected with the gate line, a first source electrode connected with the data line, and a first drain electrode connected with the first pixel electrode. The second TFT includes a second gate electrode (2162), a second source electrode (2161), and a second drain electrode (2163). The second gate electrode is connected with a gate line via a voltage dividing element. The second drain electrode is connected with the second pixel electrode.

Abstract: An LCD includes data lines, gate lines intersecting with the data lines, and pixel units. Each pixel unit is defined by a minimal area formed by two adjacent data lines and two adjacent gate lines. Each pixel unit includes a first sub pixel unit and a second sub pixel unit. The first sub pixel unit includes a first thin film transistor (TFT) and a first pixel electrode. The second sub pixel unit includes a second TFT and a second pixel electrode. A gate electrode of the first TFT is connected to the gate line, a source electrode of the first TFT is connected to the data line. A source electrode of the second TFT is connected to a same data line, and a gate electrode of the second TFT is electrically floating.

Abstract: An exemplary thin film transistor (TFT) substrate assembly includes a substrate, a plurality of gate lines disposed on an inner surface of the substrate, a plurality of data lines disposed insulated with the gate lines. The plurality of gate lines and the plurality of data lines define a plurality of pixel regions. Each pixel region includes a first switch element, a second switch element, a first pixel electrode, and a second pixel electrode. The first switch element and the second switch element are connected with a same gate line from the plurality of gate lines. The first pixel electrode is applied with data signals from a data line from the plurality of data lines via the first switch element. The second pixel electrode is applied with data signals from the data line from the plurality of data lines via the second switch element and a voltage dividing element.

Abstract: An exemplary liquid crystal display (100) includes gate lines (122), and data lines (123) cooperatively defining pixel units. Each pixel unit includes a first thin film transistor (TFT) (125), a second TFT (126), a first pixel electrode (127), and a second pixel electrode (128). Gate electrodes of the two TFTs are connected to one of the gate lines. A source electrode of the first TFT is connected to one of the data lines. A drain electrode of the first TFT is connected to the first pixel electrode. A source electrode of the second TFT is connected to the first pixel electrode. A drain electrode of the second TFT is connected to the second pixel electrode. A channel width/length ratio of the second TFT is such that a voltage of the drain electrode thereof is less than a voltage of the source electrode thereof when the second TFT is switched on.

Abstract: An exemplary liquid crystal panel (20) includes a first substrate (22), a second substrate (24) facing toward the first substrate (22), a liquid crystal layer (23) sandwiched between the two substrates, and a plurality of the conductive adhesive blocks (225) in the non-displaying region. The first substrate includes a non-displaying region (222). A transparent conductive layer (226) is disposed at a surface of the first substrate and capable of transmitting a common voltage signal to the liquid crystal layer. The first substrate at the non-displaying region includes protrusions (253) defining a plurality of gaps (254) therebetween. The transparent conductive layer covers the protrusions including parts of the protrusions defining the gaps. The conductive adhesive blocks contact the transparent conductive layer at the non-displaying region.