Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Abstract: A method comprising providing at least one dielectric layer above a semiconductor substrate, the at least one dielectric layer having a top surface and a bottom surface; forming a photoresist layer on the top surface of the at least one dielectric layer; providing a single photomask having at least one first pattern corresponding to a conductive via and at least one second pattern corresponding to a conductive trace; patterning the photoresist layer using the single photomask, for forming a trench in the photoresist corresponding to the conductive trace and an opening in a bottom surface of the trench corresponding to the via with a single photo exposure step; and etching the dielectric through the photoresist layer to form the trench and via therein. This application also relates to photomasks for use in the methods of this application.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

Abstract: A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

Abstract: A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

Abstract: A method of forming an intermetal dielectric (IMD) layer. At least one metal wire is formed on a substrate. A filling oxide layer is formed on the substrate and the metal wire. The surface of the filling oxide layer is smoothed. A first silicon-rich oxide layer is formed on the filling oxide layer, where the refractive index (RI) of the first silicon-rich oxide layer is 1.6˜1.64. A second silicon-rich oxide layer is formed on the first silicon-rich oxide layer, where the refractive index of the second silicon-rich oxide layer is 1.49˜1.55. According to the present method, the diffusion of mobile hydrogen ions is blocked by manufacture with dual silicon-rich oxide layers.

Abstract: A method of forming a memory device having a self-aligned contact is disclosed. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a silicon nitride layer on the floating poly gate layer, and forming a photoresist layer on the silicon nitride layer. The method further includes etching the silicon nitride layer and the floating poly gate layer using the photoresist layer as an etch mask, forming an oxide layer over the exposed areas, removing the photoresist layer and the silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: A method of reducing charge loss for nonvolatile memory. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate, and a thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining on the semiconductor substrate from prior manufacturing processes. Finally, a metal layer is formed on the dielectric layer.

Abstract: A fabrication method for a cobalt-salicide contact is described. A deep sub-micron contact opening is formed on a substrate. A silicon nitride spacer is further formed on the contact sidewall. A cobalt layer is further deposited in the contact opening, followed by sequentially forming an ionized metal plasma titanium layer and a chemical vapor deposited titanium nitride layer. A first rapid thermal process is performed and a wet etching is performed to remove the titanium/titanium nitride layer. A second rapid thermal process is performed, followed by filling the contact opening with a conductive layer.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: A fabrication method for a cobalt-salicide contact is described. A deep sub-micron contact opening is formed on a substrate. A silicon nitride spacer is further formed on the contact sidewall. A cobalt layer is further deposited in the contact opening, followed by sequentially forming an ionized metal plasma titanium layer and a chemical vapor deposited titanium nitride layer. A first rapid thermal process is performed and a wet etching is performed to remove the titanium/titanium nitride layer. A second rapid thermal process is performed, followed by filling the contact opening with a conductive layer.

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: A method of forming an intermetal dielectric (IMD) layer. At least one metal wire is formed on a substrate. A filling oxide layer is formed on the substrate and the metal wire. The surface of the filling oxide layer is smoothed. A first silicon-rich oxide layer is formed on the filling oxide layer, where the refractive index (RI) of the first silicon-rich oxide layer is 1.6˜1.64. A second silicon-rich oxide layer is formed on the first silicon-rich oxide layer, where the refractive index of the second silicon-rich oxide layer is 1.49˜1.55. According to the present method, the diffusion of mobile hydrogen ions is blocked by manufacture with dual silicon-rich oxide layers.