Abstract: A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: The invention provides a method for forming a semiconductor gate, by forming spacers to isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby preventing single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate. After a cap layer is formed on a conductive structure over the substrate, a HDP dielectric layer is formed exposing the cap layer. A top of the HDP dielectric layer is higher than a top of the first conductive layer. After removing the cap layer to form a recess between the HDP dielectric layer and on the conductive structure, spacers are formed on sidewalls of the recess. Afterwards, a conductive layer is formed and connected to the conductive structure.

Abstract: A method of eliminating weakness caused by high-density plasma (HDP) dielectric layer is provided. Before forming the HDP dielectric layer, a hot thermal oxide (HTO) layer is previously formed on the semiconductor substrate to serve as a buffer layer. The HTO layer eliminates the defect between the HDP dielectric layer and a cap nitride layer and releases the stress therebetween, and thereby preventing bit line leakage issue.

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern is partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: The method of forming a plurality of contact holes on a semiconductor substrate using multiple-step etching process is disclosed herein. A semiconductor substrate is provided having a plurality of semiconductor devices and a plurality of isolation regions formed thereon. A silicon oxide layer is formed on the plurality of semiconductor devices, the plurality of isolation regions, and the semiconductor substrate. An etching stop layer is formed on the silicon oxide layer followed by depositing an interlevel dielectric layer. A photoresist layer is pattern on the interlevel dielectric layer to define contact regions. A first etching process is performed to create a plurality of contact holes in the interlevel dielectric layer until exposing portions of the etching stop layer. A second etching process is performed to create the plurality of contact holes through the etching stop layer.