Abstract: The present disclosure discloses a memory write operation apparatus to perform write operation on a selected memory unit coupled to two bit lines that includes a coupling capacitor, a charge sharing circuit, a write operation driving circuit, a charging circuit and a negative voltage coupling circuit. The charge sharing circuit electrically couples a first terminal of the coupling capacitor and a first bit line to receive charges therefrom to perform charging. The negative voltage coupling circuit electrically couples the first terminal of the coupling capacitor to a ground terminal during a negative voltage generation time period such that a second terminal of the coupling capacitor couples a negative voltage to the first bit line to perform write operation.

Abstract: An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.

Abstract: An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.

Abstract: The present disclosure discloses a memory write operation apparatus to perform write operation on a selected memory unit coupled to two bit lines that includes a coupling capacitor, a charge sharing circuit, a write operation driving circuit, a charging circuit and a negative voltage coupling circuit. The charge sharing circuit electrically couples a first terminal of the coupling capacitor and a first bit line to receive charges therefrom to perform charging. The negative voltage coupling circuit electrically couples the first terminal of the coupling capacitor to a ground terminal during a negative voltage generation time period such that a second terminal of the coupling capacitor couples a negative voltage to the first bit line to perform write operation.

Abstract: An image detecting method, comprising: controlling a synchronizing controller to transmit a first activating signal to a light source controller; controlling the light source controller to control at least one light source to generate a predetermined radiating pattern, and controlling the light source controller to transmit back a first responding signal to the synchronizing controller when the light source controller receives the first activating signal; and controlling an image sensor to start an image detecting when the synchronizing controller receives the first responding signal.

Abstract: An interactive imaging system includes an image system and a remote controller. The image system includes at least one reference beacon, a receiving unit and a host. The at least one reference beacon emits light in an emission pattern. The receiving unit is configured to receive a packet data. The host controls an enable time of the at least one reference beacon according to the packet data. The remote controller includes an image sensor and a transmission unit. The image sensor captures the light emitted from the at least one reference beacon at a sampling period. The transmission unit sends the packet data corresponding to the sampling period of the image sensor.

Abstract: This disclosure provides a content addressable memory which includes: a data memory cell for storing a data bit; a mask memory cell for storing a mask bit; and a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected to at least one function bit line for receiving a search bit signal, and connected to the data memory cell and the mask memory cell for receiving the data bit and the mask bit; wherein the data memory cell is connected to a data-use write word line for receiving a data-use write word signal, the mask memory cell is connected to a mask-use write word line for receiving a mask-use write word signal, so as to decide whether a write bit signal can be written into the data bit and the mask bit through a pair of write bit lines.

Abstract: This disclosure provides a content addressable memory which includes: a data memory cell for storing a data bit; a mask memory cell for storing a mask bit; and a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected to at least one function bit line for receiving a search bit signal, and connected to the data memory cell and the mask memory cell for receiving the data bit and the mask bit; wherein the data memory cell is connected to a data-use write word line for receiving a data-use write word signal, the mask memory cell is connected to a mask-use write word line for receiving a mask-use write word signal, so as to decide whether a write bit signal can be written into the data bit and the mask bit through a pair of write bit lines.

Abstract: An image detecting method, comprising: controlling a synchronizing controller to transmit a first activating signal to a light source controller; controlling the light source controller to control at least one light source to generate a predetermined radiating pattern, and controlling the light source controller to transmit back a first responding signal to the synchronizing controller when the light source controller receives the first activating signal; and controlling an image sensor to start an image detecting when the synchronizing controller receives the first responding signal.

Abstract: An interactive imaging system includes an image system and a remote controller. The image system includes at least one reference beacon, a receiving unit and a host. The at least one reference beacon emits light in an emission pattern. The receiving unit is configured to receive a packet data. The host controls an enable time of the at least one reference beacon according to the packet data. The remote controller includes an image sensor and a transmission unit. The image sensor captures the light emitted from the at least one reference beacon at a sampling period. The transmission unit sends the packet data corresponding to the sampling period of the image sensor.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.