SRAM write assist device and method
An SRAM write assist device includes: a power circuit supplying power to an SRAM-cells column and then stopping supplying power to make the voltage of a power-receiving terminal of the SRAM-cells column floating; a write driving circuit coupling a bit line of the SRAM-cells column with a ground terminal according to a data signal in a write drive phase; a charge sharing circuit coupling the power-receiving terminal with the first terminal of a capacitor to lower this terminal's floating voltage by charge sharing in a charge sharing phase; a charging circuit including a switch turned on to charge the capacitor with an operating voltage in a charge phase; and a negative-voltage coupling circuit including the capacitor whose first and second terminals are coupled to a ground terminal and the bit line respectively to lower the voltage of the bit line by charge sharing in a negative-voltage generation phase.
The present invention relates to a static random access memory (SRAM), especially to an SRAM write assist device and method.
2. Description of Related ArtAs the semiconductor processes develop, it becomes much harder to ensure the write capability of a static random access memory (SRAM). This is because a pass-gate transistor (e.g., PG0/PG1 of
For solving the aforementioned problems, there are two kinds of conventional techniques as follows:
- (1) Negative Bit-Line (NBL) technique: This technique can increase the conducted current of a pass-gate transistor of an SRAM cell to improve its write capability. The principle of the NBL technique is to generate a negative voltage by capacitive coupling when the voltage of a bit line of an SRAM cell is pulled down to 0V in the late stage of a write cycle, and then provide the negative voltage for the bit line by charge sharing to increase the voltage drop (VGS) between the gate and source of a pass-gate transistor of the SRAM cell; accordingly, the pass-gate transistor's conducting capability can be improved, the conducted current of the pass-gate transistor can be greater than the conducted current of a pull-up transistor of the SRAM cell firmly, and the voltage at a storage node of the SRAM cell can be pulled down to 0V to complete the write operation.
FIG. 2 shows a conventional write assist circuit 202 using the NBL technique and a conventional SRAM write circuit 204. The circuit labels/symbols ofFIG. 2 are illustrated with Table 2 below while some common circuit components and symbols (e.g., transistors, inverters, and ground terminals) are not described in detail here.FIG. 3 shows a timing diagram of the signals inFIG. 2 , wherein the vertical dashed lines inFIG. 3 are reference lines indicative of time alignment. The problems of the above-mentioned NBL technique include: the capacitance of the charge sharing capacitor (CSC) should be great enough to match the parasitic capacitors caused by different bit lines with different lengths, so that the voltages of the bit lines (BLT/BLB) can be pulled down to a level low enough. However, the CSC should be fully charged and discharged in every write cycle, and thus a greater capacitance of the CSC can bring a higher power consumption. Several NBL techniques are found in the following U.S. patents/patent application publications: U.S. Pat. Nos. 8,233,342; 8,363,453; 9,070,432; US20070081379A1.
- (2) Technique for decreasing the power voltage for SRAM cells (hereafter referred to as voltage decrease technique): The voltage decrease technique can reduce the conducted current of a pull-up transistor to make a write operation easier. The principle of this technique is to decrease or stop supplying the power voltage (e.g., one of VDDC0˜VDDCn-1 in
FIG. 4 ) for a selected column of SRAM cells so that the conducted current of a pass-gate transistor is more likely to be higher than the conducted current of a pull-up transistor and thereby the voltage of the storage node can be pulled down to 0V to complete the write operation.FIG. 4 shows a conventional write assist circuit 410 (power module) using the voltage decrease technique included in a conventional SRAM write circuit 400;FIG. 4 also shows an embodiment of a power cell 412 in the write assist circuit 410. The circuit and signal labels/symbols are illustrated with Table 3 below while some common circuits and symbols (e.g., transistors and ground terminals) are not described in detail here.FIG. 5 shows a timing diagram of the signals inFIG. 4 , wherein the vertical dashed lines inFIG. 5 are reference lines indicative of time alignment. The problems of the above-mentioned voltage decrease technique include: reducing or stopping supplying the voltage for a column of SRAM cells (e.g., reducing the voltage for the column of SRAM cells by a threshold voltage of a diode as mentioned in the US patent of patent number U.S. Pat. No. 6,549,453) may affect the column of SRAM cells' capability of locking up data. Several kinds of voltage decrease techniques are found in the following US patents/patent application publications: U.S. Pat. Nos. 6,549,453; 7,324,368; 7,596,012; 8,630,132; 7,835,217; US2007/0121370.
An object of the present disclosure is to provide a static random access memory (SRAM) write assist device and method.
An embodiment of the SRAM write assist device of the present disclosure includes a power circuit, a write driving circuit, a charge sharing circuit, a coupling-capacitor charging circuit, and a negative voltage coupling circuit. The power circuit is configured to supply a power voltage to a column of SRAM cells according to a power supply selection signal in a write preparation phase, and then stop supplying the power voltage to the column of SRAM cells according to the power supply selection signal to let a voltage at a power-receiving terminal of the column of SRAM cells be in a floating state. The write driving circuit is coupled between the column of SRAM cells and a negative voltage coupling circuit, and configured to be turned on according to a data signal in a write drive phase to couple a bit line of the column of SRAM cells with a first low voltage terminal through the negative voltage coupling circuit, which consequently pulls down a voltage of the bit line of the column of SRAM cells to a voltage of the first low voltage terminal. The charge sharing circuit is coupled between the power circuit and the negative voltage coupling circuit, and configured to be turned on according to a charge sharing control signal in a charge sharing phase to couple the power-receiving terminal of the column of SRAM cells with a first terminal of a charge sharing capacitor included in the negative voltage coupling circuit, which consequently lowers the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor. The coupling-capacitor charging circuit is used for charging the charge sharing capacitor, and includes a charge switch coupled between an operation voltage terminal and the first terminal of the charge sharing capacitor; the charge switch is configured to be turned on according to the charging sharing control signal and a first switch signal in a charge phase and thereby let the charge sharing capacitor be charged with a voltage at the operation voltage terminal, wherein the charge sharing circuit is turned off according to the charging sharing control signal in the charge phase. The negative voltage coupling circuit includes the aforementioned capacitor, wherein the first terminal of the charge sharing capacitor is coupled to a second low voltage terminal in a negative voltage generation phase, and a second terminal of the charge sharing capacitor is coupled to the bit line of the column of SRAM cells through the write driving circuit in the negative voltage generation phase to pull down the voltage of the bit line of the column of SRAM cells. In the negative voltage generation phase, the charge switch is turned off, and a path for coupling the bit line of the column of SRAM cells with the first low voltage terminal through the negative voltage coupling circuit is shut off.
An embodiment of the SRAM write assist method includes the following steps: in a write preparation phase, supplying a power voltage to a column of SRAM cells according to a power supply selection signal, and then stopping supplying the power voltage to the column of SRAM cells according to the power supply selection signal to let a voltage at a power-receiving terminal of the column of SRAM cells be in a floating state; in a write drive phase, switching on a first path between the column of SRAM cells and a voltage coupling circuit according to a data signal to couple a bit line of the column of SRAM cells with a first low voltage terminal through the voltage coupling circuit and thereby pull down a voltage of the bit line of the column of SRAM cells to a voltage of the first low voltage terminal; in a charge sharing phase, switching on a second path between the power-receiving terminal of the column of SRAM cells and a first terminal of a charge sharing capacitor included in the voltage coupling circuit according to a charge sharing control signal to lower the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor; in a charge phase, switching on a third path between an operation voltage terminal and the first terminal of the charge sharing capacitor according to the charge sharing control signal and a first switch signal to charge the charge sharing capacitor with a voltage at the operation voltage terminal, wherein in the charge phase the second path between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor is shut off; and in a voltage generation phase, coupling the first terminal of the charge sharing capacitor with a second low voltage terminal and coupling a second terminal of the charge sharing capacitor with the bit line of the column of SRAM cells to pull down the voltage of the bit line of the column of SRAM cells, wherein in the voltage generation phase the third path between the operation voltage terminal and the first terminal of the charge sharing capacitor is shut off and the first path for coupling the bit line of the column of SRAM cells with the first low voltage terminal through the voltage coupling circuit is shut off.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.
The present disclosure includes a static random access memory (SRAM) write assist device and method. In comparison with the prior art, the device and method can fulfill the write assist function with a charge sharing capacitor having smaller capacitance and can reduce power consumption.
In a write preparation phase, the power circuit 610 is configured to supply a power voltage (i.e., VDDCi which is one of VDDC0˜VDDCn-1) to a power-receiving terminal of a column of SRAM cells (e.g., a column of SRAM cells including the SRAM Celli, wherein an example of the SRAM Celli is one of the SRAM Cell0˜SRAM Celln-1 in
The write driving circuit 620 is coupled between the column of SRAM cells and the negative voltage coupling circuit 650, and includes two transistors MN0, MN1 that are used for receiving two data signals DIT, DIB, wherein DIB is equivalent to an inverted signal of DIT. In a write drive phase, the write driving circuit 620 is turned on according to the data signal (DIT/DIB) to couple a bit line (BLTi/BLBi) of the column of SRAM cells with a first low voltage terminal (e.g., the ground terminal coupled with the transistor MND in
The charge sharing circuit 630 is coupled between the power circuit 610 and the negative voltage coupling circuit 650. In a charge sharing phase, the charge sharing circuit 630 is turned on according to a charge sharing control signal (WCCE) to let the power-receiving terminal of the column of SRAM cells be coupled to a first terminal (e.g., a positive-electrode terminal) of a charge sharing capacitor (CSC) of the negative voltage coupling circuit 650 through a node (NCC), and thereby the voltage (VDDCi) at the power-receiving terminal of the column of SRAM cells is lowered by the charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor. Since the voltage at the power-receiving terminal of the column of SRAM cells is decreased, it will be easier to write data into the to-be-written SRAM cell (i.e., SRAM Celli). In the embodiment of
The coupling-capacitor charging circuit 640 includes a charge switch (MPL). The charge switch is coupled between an operation voltage terminal (VDD terminal) and the first terminal of the charge sharing capacitor (CSC), and is configured to be turned on according to the charge sharing control signal (WCCE) and a first switch signal (e.g., an inverted signal of a write assist control signal WAE as shown in
The negative voltage coupling circuit 650 includes the aforementioned charge sharing capacitor (CSC), wherein the first terminal of the charge sharing capacitor is coupled to a second low voltage terminal (e.g., the ground terminal that is coupled with the transistor MNU in
In the embodiment of
An exemplary timing diagram of the signals in
It is noted that the write driving circuit 620 is further coupled to a write bit line pre-charge circuit (e.g., the write bit line pre-charge circuit 440 in
- step S910: in a write preparation phase, supplying a power voltage to a column of SRAM cells according to a power supply selection signal, and then stopping supplying the power voltage to the column of SRAM cells according to the power supply selection signal to let a voltage at a power-receiving terminal of the column of SRAM cells be in a floating state;
- step S920: in a write drive phase, switching on a first path between the column of SRAM cells and a voltage coupling circuit according to a data signal to couple a bit line of the column of SRAM cells to a first low voltage terminal through the voltage coupling circuit and thereby pull down a voltage of the bit line of the column of SRAM cells to a voltage of the first low voltage terminal;
- step S930: in a charge sharing phase, switching on a second path between the power-receiving terminal of the column of SRAM cells and a first terminal of a charge sharing capacitor included in the voltage coupling circuit according to a charge sharing control signal to lower the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor;
- step S940: in a charge phase, switching on a third path between an operation voltage terminal and the first terminal of the charge sharing capacitor according to the charge sharing control signal and a first switch signal to charge the charge sharing capacitor with a voltage at the operation voltage terminal, wherein in the charge phase the second path between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor is shut off; and
- step S950: in a voltage generation phase, coupling the first terminal of the charge sharing capacitor with a second low voltage terminal and coupling a second terminal of the charge sharing capacitor with the bit line of the column of SRAM cells to pull down the voltage of the bit line of the column of SRAM cells, wherein in the voltage generation phase the third path between the operation voltage terminal and the first terminal of the charge sharing capacitor is shut off and the first path for coupling the bit line of the column of SRAM cells with the first low voltage terminal through the voltage coupling circuit is shut off.
It is noted that the steps of embodiment of
Since those of ordinary skill in the art can appreciate the detail and modification of the embodiment of
It is noted that people of ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable, which implies that the present invention can be implemented in various ways.
To sum up, the SRAM write assist device and method of the present disclosure can fulfill the write assist function with a charge sharing capacitor having smaller capacitance and can reduce power consumption in comparison with the prior art.
The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of present invention are all consequently viewed as being embraced by the scope of the present invention.
Claims
1. A static random access memory (SRAM) write assist device, comprising:
- a power circuit configured to supply a power voltage to a column of SRAM cells according to a power supply selection signal in a write preparation phase, and then stop supplying the power voltage to the column of SRAM cells according to the power supply selection signal to let a voltage at a power-receiving terminal of the column of SRAM cells be in a floating state;
- a write driving circuit coupled between the column of SRAM cells and a negative voltage coupling circuit, the write driving circuit configured to be turned on according to a data signal in a write drive phase to couple a bit line of the column of SRAM cells with a first low voltage terminal through the negative voltage coupling circuit and thereby pull down a voltage of the bit line of the column of SRAM cells to a voltage of the first low voltage terminal;
- a charge sharing circuit coupled between the power circuit and the negative voltage coupling circuit, the charge sharing circuit configured to be turned on according to a charge sharing control signal in a charge sharing phase to couple the power-receiving terminal of the column of SRAM cells with a first terminal of a charge sharing capacitor included in the negative voltage coupling circuit and thereby lower the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor;
- a coupling-capacitor charging circuit for charging the charge sharing capacitor, the coupling-capacitor charging circuit including a charge switch coupled between an operation voltage terminal and the first terminal of the charge sharing capacitor, the charge switch configured to be turned on according to the charging sharing control signal and a first switch signal in a charge phase and thereby let the charge sharing capacitor be charged with a voltage at the operation voltage terminal, wherein the charge sharing circuit is turned off according to the charging sharing control signal in the charge phase; and
- the negative voltage coupling circuit including the charge sharing capacitor, wherein the first terminal of the charge sharing capacitor is coupled to a second low voltage terminal in a negative voltage generation phase, and a second terminal of the charge sharing capacitor is coupled to the bit line of the column of SRAM cells through the write driving circuit in the negative voltage generation phase to pull down the voltage of the bit line of the column of SRAM cells,
- wherein in the negative voltage generation phase the charge switch is turned off, and a path for coupling the bit line of the column of SRAM cells with the first low voltage terminal through the negative voltage coupling circuit is shut off.
2. The SRAM write assist device of claim 1, wherein the charge sharing circuit includes:
- a column selecting switch configured to be turned on according to a column selection signal in the charge sharing phase to let the power-receiving terminal of the column of SRAM cells be coupled to a charge sharing switch, wherein the column selection signal is related to the power supply selection signal; and
- the charge sharing switch configured to be turned on according to the charge sharing control signal to let the power-receiving terminal of the column of SRAM cells be coupled to the first terminal of the charge sharing capacitor.
3. The SRAM write assist device of claim 1, wherein the coupling-capacitor charging circuit includes:
- a charge control circuit configured to generate a charge control signal according to the charge sharing control signal and the first switch signal; and
- the charge switch configured to be turned on or turned off according to the charge control signal.
4. The SRAM write assist device of claim 1, wherein the negative voltage coupling circuit includes:
- a switch signal generating circuit configured to generate the first switch signal according to a write assist control signal;
- a first switch coupled between the second terminal of the charge sharing capacitor and the first low voltage terminal, the first switch configured to be turned on according to the first switch signal in the charge sharing phase and the charge phase, and configured to be turned off according to the first switch signal in the negative voltage generation phase; and
- a second switch coupled between the first terminal of the charge sharing capacitor and the second low voltage terminal, the second switch configured to be turned off according to the write assist control signal in the charge sharing phase and the charge phase, and configured to be turned on according to the write assist control signal in the negative voltage generation phase.
5. The SRAM write assist device of claim 4, wherein the first switch signal is equivalent to an inverted signal of the write assist control signal.
6. The SRAM write assist device of claim 4, wherein the switch signal generating circuit includes:
- a first inverter configured to receive the write assist control signal to generate the first switch signal; and
- a second inverter configured to receive the first switch signal to generate a second switch signal equivalent to the write assist control signal, and then output the second switch signal to the second switch.
7. A static random access memory (SRAM) write assist method, comprising:
- in a write preparation phase, supplying a power voltage to a column of SRAM cells according to a power supply selection signal, and then stopping supplying the power voltage to the column of SRAM cells according to the power supply selection signal to let a voltage at a power-receiving terminal of the column of SRAM cells be in a floating state;
- in a write drive phase, switching on a first path between the column of SRAM cells and a voltage coupling circuit according to a data signal to couple a bit line of the column of SRAM cells with a first low voltage terminal through the voltage coupling circuit and thereby pull down a voltage of the bit line of the column of SRAM cells to a voltage of the first low voltage terminal;
- in a charge sharing phase, switching on a second path between the power-receiving terminal of the column of SRAM cells and a first terminal of a charge sharing capacitor included in the voltage coupling circuit according to a charge sharing control signal to lower the voltage at the power-receiving terminal of the column of SRAM cells by charge sharing between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor;
- in a charge phase, switching on a third path between an operation voltage terminal and the first terminal of the charge sharing capacitor according to the charge sharing control signal and a first switch signal to charge the charge sharing capacitor with a voltage at the operation voltage terminal, wherein in the charge phase the second path between the power-receiving terminal of the column of SRAM cells and the first terminal of the charge sharing capacitor is shut off; and
- in a voltage generation phase, coupling the first terminal of the charge sharing capacitor with a second low voltage terminal and coupling a second terminal of the charge sharing capacitor with the bit line of the column of SRAM cells to pull down the voltage of the bit line of the column of SRAM cells, wherein in the voltage generation phase the third path between the operation voltage terminal and the first terminal of the charge sharing capacitor is shut off and the first path for coupling the bit line of the column of SRAM cells with the first low voltage terminal through the voltage coupling circuit is shut off.
8. The method of claim 7, wherein a step for switching on the second path includes:
- in the charge sharing phase switching on a path between the power-receiving terminal of the column of SRAM cells and a charge sharing switch according to a column selection signal, wherein the column selection signal is related to the power supply selection signal; and
- in the charge sharing phase turning on the charge sharing switch according to the charge sharing control signal to let the power-receiving terminal of the column of SRAM cells be coupled to the first terminal of the charge sharing capacitor.
9. The method of claim 7, further comprising:
- in the charge sharing phase switching on a fourth path between the power-receiving terminal of the column of SRAM cells and a charge sharing switch according to a column selection signal, wherein the column selection signal is related to the power supply selection signal; and
- in the charge sharing phase switching on a fifth path between the charge sharing switch and the first terminal of the charge sharing capacitor.
10. The method of claim 7, further comprising:
- generating a charge control signal according to the charge sharing control signal and the first switch signal; and
- switching on or switching off the third path between the operation voltage terminal and the first terminal of the charge sharing capacitor according to the charge control signal.
11. The method of claim 7, further comprising:
- in the charge sharing phase and the charge phase switching on a fourth path between the second terminal of the charge sharing capacitor and the first low voltage terminal according to the first switch signal;
- in the voltage generation phase switching off the fourth path;
- in the charge sharing phase and the charge phase switching off a fifth path between the first terminal of the charge sharing capacitor and the second low voltage terminal by a write assist control signal; and
- in the voltage generation phase switching on the fifth path by the write assist control signal.
12. The method of claim 11, wherein the first switch signal is equivalent to an inverted signal of the write assist control signal.
Type: Application
Filed: Jan 14, 2021
Publication Date: Nov 4, 2021
Inventor: HUNG-YU LEE (Hsinchu County)
Application Number: 17/148,608