Abstract: An anti-fuse device including a substrate, a doped region, a dielectric layer, a first contact, an anti-fuse material layer, and a second contact is provided. The doped region is located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening respectively expose the doped region. The first contact is located in the first opening. The anti-fuse material layer is located between the first contact and the doped region. The second contact is located in the second opening and is electrically connected to the doped region.

Abstract: This disclosure provides a method, an apparatus, and a non-transitory computer-readable medium for radio resource allocation for a terrestrial network (TN) cell. In the method, the TN cell is determined to be outside a coverage of a first non-terrestrial network (NTN) cell. In response to the TN cell being outside the coverage of the first NTN cell, a radio resource is allocated to the TN cell based on a radio resource of the first NTN cell.

Abstract: A method for performing radio resource allocation in a TN-NTN mixed system is provided. The system includes a satellite that covers an NTN cell, and a plurality of TN base stations (TN BSs) within a coverage of the satellite. The NTN cell serves a plurality of NTN user equipments (NTN UEs). The method includes dividing the plurality of NTN UEs into X NTN UE groups; partitioning a radio resource into M parts, where M?X; dividing the plurality of TN BSs into M TN BS groups; deciding radio resource allocation regarding the plurality of NTN UEs, by allocating an i-th part of the radio resource to an i-th NTN UE group, where i=1, 2, . . . , X; and deciding radio resource allocation regarding the plurality of TN BSs, by allocating a sum of a j-th to an M-th parts of the radio resource to a j-th TN BS group, where j=1, 2, . . . , M.

Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

Abstract: According to an aspect of the disclosure, the disclosure is directed to a wireless communication apparatus on a vehicle. The wireless communication the apparatus includes (not limited to): first wireless transceiver configured to transmit and receive data on a first communication path; a second wireless transceiver configured to transmit and receive data on a second communication path; and a processor electrically connected to the first wireless transceiver and the second wireless transceiver and configured at least to: establish, as a default mean of communication, multiple communication paths; transmit by the first wireless transceiver, as the default mean of communication, a first data packet to the network located outside of the vehicle on a first communication path; and transmit by the second wireless transceiver, as the default mean of communication, a first duplicated data packet of the first data packet to the network on a second communication path.

Abstract: A method of inter-cell coordination for intelligent reflecting surface (IRS) assisted wireless network is provided. The method includes: receiving mode information corresponding to a first intelligent reflecting surface and a second intelligent reflecting surface; performing a channel measurement according to the mode information to generate a measurement report; transmitting the measurement report to a serving base station; and performing data transmission via the first intelligent reflecting surface and the second intelligent reflecting surface configured according to the measurement report.

Abstract: A method of channel measurement for intelligent reflecting surface assisted wireless network and a base station (BS) using the same method are provided. The method includes: transmitting a measurement configuration comprising mode information of an intelligent reflecting surface to a user equipment; receiving a measurement report corresponding to the measurement configuration from the user equipment, wherein the measurement report corresponds to a channel between the user equipment and the intelligent reflecting surface; and outputting a command according to the measurement report.

Abstract: A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

Abstract: An anti-fuse device including a substrate, a doped region, a dielectric layer, a first contact, an anti-fuse material layer, and a second contact is provided. The doped region is located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening respectively expose the doped region. The first contact is located in the first opening. The anti-fuse material layer is located between the first contact and the doped region. The second contact is located in the second opening and is electrically connected to the doped region.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.

Abstract: A semiconductor structure includes a semiconductor substrate including a first active region and a chop region. The semiconductor structure also includes a source/drain region disposed in the first active region, an isolation structure disposed in the chop region, and a gate structure extending at least across the isolation structure in the chop region. The gate structure includes a gate electrode layer and a gate lining layer lining on the gate electrode layer. The gate lining layer includes a first portion having an upper surface that is lower than a bottom surface of the source/drain region.

Abstract: A user equipment (UE) includes a processor and a transmitter. The processor performs a neural network computation to generate a plurality of neural network computation results, wherein the neural network computation results are included in a data packet, and the neural network computation results are intermediate data of the neural network computation. The transmitter transmits the data packet to a base station. The data packet includes a descriptor and the descriptor includes parameters and settings corresponding to the neural network computation results.

Abstract: A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductive layer and a metal layer. The first conductive layer is located on the first electrode. The metal layer is located on the first conductive layer. The metal layer exposes a portion of the first conductive layer. The insulating layer is located between the first electrode and the second electrode.

Abstract: A semiconductor device including a substrate and a capacitor is provided. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductive layer and a metal layer. The first conductive layer is located on the first electrode. The metal layer is located on the first conductive layer. The metal layer exposes a portion of the first conductive layer. The insulating layer is located between the first electrode and the second electrode.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: A base station of a telecommunication network is provided. The base station includes a wired transceiver, a wireless transceiver, and a controller. The wired transceiver provides wired communication with a first Time-Sensitive Networking (TSN) domain outside the telecommunication network. The wireless transceiver provides wireless Time-Sensitive Communication (TSC) with a User Equipment (UE). A controller is configured to receive first TSN clock information from the first TSN domain via the wired transceiver, and schedule a transmission of the first TSN clock information to the UE via the wireless transceiver.

Abstract: A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.