Patents by Inventor Hwa-sung Rhee

Hwa-sung Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190221564
    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.
    Type: Application
    Filed: March 27, 2019
    Publication date: July 18, 2019
    Inventors: Ju-Youn KIM, Hyun-Jo KIM, Hwa-Sung RHEE
  • Patent number: 10276567
    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Hyun-Jo Kim, Hwa-Sung Rhee
  • Patent number: 10074572
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
  • Publication number: 20180254188
    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.
    Type: Application
    Filed: May 2, 2018
    Publication date: September 6, 2018
    Inventors: Yoon-Hae KIM, Hwa-sung RHEE, Keun-hwi CHO
  • Patent number: 10032886
    Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Yup Chung, Hyun-Jo Kim, Seong-Yul Park, Se-Wan Park, Jong-Mil Youn, Jeong-Hyo Lee, Hwa-Sung Rhee, Hee-Don Jeong, Ji-Yong Ha
  • Patent number: 9984886
    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
  • Patent number: 9922979
    Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Jong-shik Yoon, Hwa-sung Rhee, Hee-don Jeong, Je-Min Yoo, Kyu-man Cha, Jong-mil Youn, Hyun-jo Kim
  • Publication number: 20180012814
    Abstract: A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.
    Type: Application
    Filed: April 27, 2017
    Publication date: January 11, 2018
    Inventors: Zhan ZHAN, Hwa Sung RHEE, Myung Jo CHUN
  • Patent number: 9754789
    Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee, Byung-Sung Kim
  • Publication number: 20170221770
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Jae-yup Chung, Yoon-seok LEE, Hyun-jo KIM, Hwa-sung RHEE, Hee-don JEONG, Se-wan PARK, Bo-cheol JEONG
  • Patent number: 9673330
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
  • Publication number: 20160380075
    Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 29, 2016
    Inventors: Jae-Yup CHUNG, Hyun-Jo KIM, Seong-Yul PARK, Se-Wan PARK, Jong-Mil YOUN, Jeong-Hyo LEE, Hwa-Sung RHEE, Hee-Don JEONG, Ji-Yong HA
  • Publication number: 20160372467
    Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.
    Type: Application
    Filed: February 3, 2016
    Publication date: December 22, 2016
    Inventors: Ju-Youn KIM, Hyun-Jo KIM, Hwa-Sung RHEE
  • Patent number: 9496192
    Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: November 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Lim Kang, Min-Ho Kwon, Wei-Hua Hsu, Sang-Hyun Woo, Hwa-Sung Rhee, Jun-Suk Choi
  • Publication number: 20160322304
    Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.
    Type: Application
    Filed: January 20, 2016
    Publication date: November 3, 2016
    Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
  • Publication number: 20160284706
    Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.
    Type: Application
    Filed: February 3, 2016
    Publication date: September 29, 2016
    Inventors: Jae-yup CHUNG, Jong-shik YOON, Hwa-sung RHEE, Hee-don JEONG, Je-Min YOO, Kyu-man CHA, Jong-mil YOUN, Hyun-jo KIM
  • Publication number: 20160247876
    Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.
    Type: Application
    Filed: December 11, 2015
    Publication date: August 25, 2016
    Inventors: Jae-yup Chung, Yoon-seok LEE, Hyun-jo KIM, Hwa-sung RHEE, Hee-don JEONG, Se-wan PARK, Bo-cheol JEONG
  • Patent number: 9412693
    Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 9, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee
  • Publication number: 20160172361
    Abstract: Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: Hwa-Sung Rhee, Seung-Chul LEE, Chul-Wan AN, Henry K. UTOMO, Seong-Dong KIM
  • Patent number: 9318573
    Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate insulation layer formed on a silicon substrate, at least one nanorod embedded in the gate insulation layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate insulation layer between the source electrode and the drain electrode.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Wook Moon, Joong S. Jeon, Jung-hyun Lee, Nae-In Lee, Yeon-Sik Park, Hwa-Sung Rhee, Ho Lee, Se-Young Cho, Suk-Pil Kim