Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.

Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.

Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.

Abstract: A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node.

Abstract: A pumping circuit includes a cross-coupled charge pump circuit including first and second capacitors configured to pump an input voltage in response to a first clock signal and to an inverted first clock signal and a plurality of transistors configured to one of transfer the input voltage to the first and second capacitors and to transfer a pumping voltage to an output node, and a switching voltage supply circuit configured to supply switching voltages to gates of the plurality of transistors to enable the transfer of the input voltage and the pumping voltage.

Abstract: A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on the selected word line, and a control circuit configured to control the peripheral circuit to perform the program operation by applying a program voltage to a word line selected for the program operation, applying a ground voltage to a word line of which a program operation has been completed and applying a pass voltage to the other word lines.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.

Abstract: A semiconductor memory device includes a power block configured to generate an internal voltage based on an external voltage which is applied through a power pad; a circuit block configured to operate according to the internal voltage and drive memory cells; and a CAM (content addressed memory) block configured to operate according to the external voltage and store setting information necessary for driving of the memory cells.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.

Abstract: A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on the selected word line, and a control circuit configured to control the peripheral circuit to perform the program operation by applying a program voltage to a word line selected for the program operation, applying a ground voltage to a word line of which a program operation has been completed and applying a pass voltage to the other word lines.

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.

Abstract: A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias voltage based on the sensed temperature.

Abstract: A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines, and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines.

Abstract: A nonvolatile semiconductor memory apparatus includes a memory cell block, a plurality of page buffers, and a reference page buffer unit. The memory cell block includes a plurality of memory cell strings each of which includes a plurality of memory cells and a dummy memory cell string which includes a plurality of dummy memory cells. The page buffers sense data stored in the memory cells and apply the sensed data to an output node. The reference page buffer unit senses the dummy memory cells and adjusts the timing to apply the values sensed by the page buffers to the output node.

Abstract: The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.

Abstract: A semiconductor memory device includes a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line, a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of the memory cells coupled to even word lines, and a second erase verify operation of the memory cells coupled to odd word lines, and an operation circuit, performing the erase operation of the memory cells, applying a first voltage to the odd and even word lines to form a channel in the vertical semiconductor layer between the odd and even word lines when the first and second erase verify operations are performed, respectively.