Abstract: A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a first voltage level, a first latch unit configured to store program data and output the stored program data to the sense node, a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state to a second voltage level, and a voltage control element configured to raise a voltage level of the sense node or drop a voltage level of the sense node to a third voltage level in response to a second control signal.

Abstract: A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation.

Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.

Abstract: A semiconductor memory device includes even page buffers coupled to even memory cells through respective even bit lines, odd page buffers coupled to odd memory cells through respective odd bit lines, first BL selectors, each configured to couple each of the even bit lines to the respective even page buffers and to couple each of the even page buffers to respective odd bit lines so that the even and odd page buffers precharge the odd bit lines in a precharge operation for the odd bit lines, and second BL selectors, each configured to couple each of the odd bit lines to the respective odd page buffers and to couple each of the odd page buffers to respective even bit lines so that the even and odd page buffers precharge the even bit lines in a precharge operation for the even bit lines.

Abstract: A method for operating a non-volatile memory device includes counting the number of consecutive verify operations performed without a precharge, sensing a temperature, and when the number of verify operations exceeds a set value of verify operations, controlling a level of a sensing bias voltage based on the sensed temperature.

Abstract: A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation.

Abstract: A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a first voltage level, a first latch unit configured to store program data and output the stored program data to the sense node, a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state to a second voltage level, and a voltage control element configured to raise a voltage level of the sense node or drop a voltage level of the sense node to a third voltage level in response to a second control signal.

Abstract: A page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.