Patents by Inventor Hwa-sung Rhee
Hwa-sung Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11183496Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.Type: GrantFiled: March 27, 2019Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Youn Kim, Hyun-Jo Kim, Hwa-Sung Rhee
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Patent number: 10622265Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.Type: GrantFiled: January 11, 2019Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Choi, Zhan Zhan, Min-Seob Kim, Ju-Hyun Kim, Sung-Gun Kang, Hwa-Sung Rhee
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Patent number: 10600702Abstract: A test element group includes a test element including a plurality of test transistors connected in series between a first node and a second node, the second node being connected to a ground node; a first transistor connected between the first node and a power supply node; and a second transistor configured to generate an output current, proportional to a voltage at the first node, and connected to the first node and the power supply node.Type: GrantFiled: October 1, 2018Date of Patent: March 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Zhan Zhan, Ju Hyun Kim, Sung Gun Kang, Hwa Sung Rhee
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Patent number: 10522430Abstract: A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.Type: GrantFiled: April 27, 2017Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Zhan Zhan, Hwa Sung Rhee, Myung Jo Chun
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Publication number: 20190385918Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.Type: ApplicationFiled: January 11, 2019Publication date: December 19, 2019Inventors: Ji-Young CHOI, Zhan ZHAN, Min-Seob KIM, Ju-Hyun KIM, Sung-Gun KANG, Hwa-Sung RHEE
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Publication number: 20190304856Abstract: A test element group includes a test element including a plurality of test transistors connected in series between a first node and a second node, the second node being connected to a ground node; a first transistor connected between the first node and a power supply node; and a second transistor configured to generate an output current, proportional to a voltage at the first node, and connected to the first node and the power supply node.Type: ApplicationFiled: October 1, 2018Publication date: October 3, 2019Inventors: Zhan Zhan, Ju Hyun Kim, Sung Gun Kang, Hwa Sung Rhee
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Patent number: 10410871Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.Type: GrantFiled: May 2, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
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Publication number: 20190221564Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.Type: ApplicationFiled: March 27, 2019Publication date: July 18, 2019Inventors: Ju-Youn KIM, Hyun-Jo KIM, Hwa-Sung RHEE
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Patent number: 10276567Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.Type: GrantFiled: February 3, 2016Date of Patent: April 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Youn Kim, Hyun-Jo Kim, Hwa-Sung Rhee
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Patent number: 10074572Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.Type: GrantFiled: April 19, 2017Date of Patent: September 11, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
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Publication number: 20180254188Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.Type: ApplicationFiled: May 2, 2018Publication date: September 6, 2018Inventors: Yoon-Hae KIM, Hwa-sung RHEE, Keun-hwi CHO
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Patent number: 10032886Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.Type: GrantFiled: June 1, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Yup Chung, Hyun-Jo Kim, Seong-Yul Park, Se-Wan Park, Jong-Mil Youn, Jeong-Hyo Lee, Hwa-Sung Rhee, Hee-Don Jeong, Ji-Yong Ha
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Patent number: 9984886Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.Type: GrantFiled: January 20, 2016Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Hae Kim, Hwa-Sung Rhee, Keun-Hwi Cho
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Patent number: 9922979Abstract: An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.Type: GrantFiled: February 3, 2016Date of Patent: March 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yup Chung, Jong-shik Yoon, Hwa-sung Rhee, Hee-don Jeong, Je-Min Yoo, Kyu-man Cha, Jong-mil Youn, Hyun-jo Kim
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Publication number: 20180012814Abstract: A semiconductor device includes first and second pads separated from each other, first and second test elements connected to the first and second pads and connected to each other in parallel between the first and second pads, a first diode connected to the first test element in series, and a second diode connected to the second test element in series.Type: ApplicationFiled: April 27, 2017Publication date: January 11, 2018Inventors: Zhan ZHAN, Hwa Sung RHEE, Myung Jo CHUN
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Patent number: 9754789Abstract: Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.Type: GrantFiled: October 8, 2014Date of Patent: September 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae Kim, Jong-Shik Yoon, Hwa-Sung Rhee, Byung-Sung Kim
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Publication number: 20170221770Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Jae-yup Chung, Yoon-seok LEE, Hyun-jo KIM, Hwa-sung RHEE, Hee-don JEONG, Se-wan PARK, Bo-cheol JEONG
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Patent number: 9673330Abstract: An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.Type: GrantFiled: December 11, 2015Date of Patent: June 6, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-yup Chung, Yoon-seok Lee, Hyun-jo Kim, Hwa-sung Rhee, Hee-don Jeong, Se-wan Park, Bo-cheol Jeong
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Publication number: 20160380075Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.Type: ApplicationFiled: June 1, 2016Publication date: December 29, 2016Inventors: Jae-Yup CHUNG, Hyun-Jo KIM, Seong-Yul PARK, Se-Wan PARK, Jong-Mil YOUN, Jeong-Hyo LEE, Hwa-Sung RHEE, Hee-Don JEONG, Ji-Yong HA
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Publication number: 20160372467Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.Type: ApplicationFiled: February 3, 2016Publication date: December 22, 2016Inventors: Ju-Youn KIM, Hyun-Jo KIM, Hwa-Sung RHEE