Patents by Inventor Hwee-Seng Jimmy Chew
Hwee-Seng Jimmy Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160268225Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: May 18, 2016Publication date: September 15, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Chee-Kian ONG
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Patent number: 9396982Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.Type: GrantFiled: November 26, 2008Date of Patent: July 19, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
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Publication number: 20160189981Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong Raymond LIM
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Patent number: 9379044Abstract: A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.Type: GrantFiled: October 20, 2012Date of Patent: June 28, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
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Patent number: 9362206Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: GrantFiled: June 23, 2014Date of Patent: June 7, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee-Kian Ong
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Publication number: 20160118349Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.Type: ApplicationFiled: December 7, 2015Publication date: April 28, 2016Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Kian-Hock LIM, Oviso Dominador Jr FORTALEZA, Shoa-Siong Raymond LIM
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Patent number: 9305868Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.Type: GrantFiled: December 22, 2014Date of Patent: April 5, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Lim, Kian-Hock Lim
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Patent number: 9301391Abstract: A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.Type: GrantFiled: November 29, 2012Date of Patent: March 29, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
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Patent number: 9287157Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.Type: GrantFiled: June 29, 2010Date of Patent: March 15, 2016Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
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Publication number: 20160013139Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.Type: ApplicationFiled: February 21, 2014Publication date: January 14, 2016Applicant: ADVANPACK SOLUTIONS PTE LTDInventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
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Patent number: 9219027Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.Type: GrantFiled: February 20, 2014Date of Patent: December 22, 2015Assignee: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim
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Publication number: 20150111345Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong LIM, Kian-Hock LIM
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Patent number: 8917521Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.Type: GrantFiled: April 28, 2011Date of Patent: December 23, 2014Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Lim, Kian-Hock Lim
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Publication number: 20140299984Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Chee-Kian ONG
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Patent number: 8846519Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.Type: GrantFiled: May 9, 2012Date of Patent: September 30, 2014Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Patent number: 8796844Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.Type: GrantFiled: September 2, 2009Date of Patent: August 5, 2014Assignee: AdvanPack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong
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Patent number: 8791583Abstract: Mold pieces (105 and 110) for molding a layer of mold compound on the interconnect side of a bumped semiconductor wafer (118) include a primary cavity (117) and secondary cavities (120) into which excess mold compound from the primary cavity (117) flows. The secondary cavities (120) include a plunger (130) that asserts a predetermined backpressure that is equal to a desired mold compound pressure on the mold compound during molding. As most of the excess mold compound in the primary cavity (117) is forced to flow into the secondary cavities (120), this advantageously leaves a relatively thin layer of mold compound on the semiconductor wafer (118), which can then be removed, for example by grinding in a relatively short time. Mold piece (105) further comprises a movable cavity bar (115) that can be moved away from mold piece (105) after molding and be cooled to detach the molded substrate that adheres to the cavity bar.Type: GrantFiled: October 4, 2002Date of Patent: July 29, 2014Assignee: Advanced Systems Automation Ltd.Inventors: Hwee Seng Jimmy Chew, Dingwei Xia
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Patent number: 8766438Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.Type: GrantFiled: September 1, 2009Date of Patent: July 1, 2014Assignee: Advanpack Solutions PTE Ltd.Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Kee Kwang Lau
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Publication number: 20140167240Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: ADVANPACK SOLUTIONS PTE LTD.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock LIM, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim
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Patent number: 8709874Abstract: A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.Type: GrantFiled: August 31, 2011Date of Patent: April 29, 2014Assignee: Advanpack Solutions Pte Ltd.Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Jr Fortaleza, Shoa-Siong Raymond Lim