Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

Abstract: A ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A coercive electric field of the first ferroelectric material layer is different from that of the second ferroelectric material layer, and the electrical floating layer comprises a conductive material.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Abstract: In an embodiment, a ferroelectric memory element includes a first electrode layer, a ferroelectric structure disposed on the first electrode layer, and a second electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.

Abstract: A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Abstract: A ferroelectric memory device according to an embodiment of the present disclosure includes a substrate, a ferroelectric material layer disposed on the substrate, a gate electrode layer disposed on the ferroelectric material layer, and a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer.

Abstract: In a method of operating a ferroelectric device, a ferroelectric device including a first electrode layer, a ferroelectric layer and a second electrode layer that are sequentially disposed is provided. A first remanent polarization is written in the ferroelectric layer. An operating voltage is applied between the first and second electrode layers to write a second remanent polarization having a polarization value different from a polarization value of the first remanent polarization in the ferroelectric layer. An amplitude of the operating voltage varies within a voltage application time period and varies in a set voltage range.

Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.

Abstract: A ferroelectric semiconductor device of the present disclosure includes a substrate, a ferroelectric layer disposed on the substrate, an electric field control layer that is disposed on the ferroelectric layer and has a predetermined internal electric field formed without the application of an external electric power to alter the magnitude of a coercive electric field of the ferroelectric layer, and a gate electrode layer disposed on the electric field control layer.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Abstract: A ferroelectric semiconductor device of the present disclosure includes a substrate having a channel structure, a trench pattern having a bottom surface and a sidewall surface in the channel structure, a dielectric layer disposed on the bottom surface and the sidewall surface of the trench pattern, and a gate electrode layer disposed on the dielectric layer. The dielectric layer includes a ferroelectric layer pattern and a non-ferroelectric layer pattern that are disposed along the sidewall surface of the trench pattern.

Abstract: A ferroelectric memory device includes a substrate, a ferroelectric layer, a variable resistive memory layer and a gate electrode which are sequentially stacked on a surface of the substrate. The ferroelectric layer has any one of a plurality of different remanent polarization values depending on a resistive state of the variable resistive memory layer.

Abstract: A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.

Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. Further, the ferroelectric memory device includes a gate electrode layer disposed on the superlattice structure.

Abstract: A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer. The recombination induction layer includes a material containing holes acting as a majority carrier.

Abstract: A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench.

Abstract: In an embodiment, a ferroelectric memory device includes a semiconductor substrate, a first ferroelectric memory cell transistor of NMOS type disposed in a first region of the semiconductor substrate, and a second ferroelectric memory cell transistor of PMOS type disposed in a second region adjacent to the first region of the semiconductor substrate. A first gate electrode layer of the first ferroelectric memory cell transistor and a second gate electrode layer of the second ferroelectric memory cell transistor are electrically connected to each other.

Abstract: A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a channel layer disposed on the semiconductor substrate, a ferroelectric layer disposed on the channel layer, and a gate electrode layer disposed on the ferroelectric layer. The channel layer includes an epitaxial film.