Abstract: A nonvolatile memory device according to an embodiment includes a first electrode layer, a first barrier layer, a resistive memory layer, a second barrier layer and a second electrode layer that are sequentially disposed. The resistive memory layer comprises a Mott material, the Mott material having a resistivity that varies depending on an externally applied electric field.

Abstract: A ferroelectric memory device according to an embodiment includes a base conduction layer, a channel layer extending in a vertical direction from the base conduction layer, a ferroelectric layer disposed on the channel layer, a plurality of ferroelectric memory cell transistor stacked in a vertical direction on the base conduction layer, a control transistor disposed over the plurality of ferroelectric memory cell transistors, and a bit line pattern electrically connected to the channel layer.

Abstract: In a method of manufacturing a ferroelectric device, a substrate is provided. A ferroelectric material film is formed over the substrate. A crystallization seed film is formed over the ferroelectric material film. The ferroelectric material film is heat-treated to covert the ferroelectric material film into a crystalline ferroelectric film. The crystallization seed film is removed to expose the crystalline ferroelectric film. An electrode film is formed over the ferroelectric film.

Abstract: A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.

Abstract: In a method of operating a ferroelectric device, a ferroelectric device including a first electrode layer, a ferroelectric layer and a second electrode layer that are sequentially disposed is provided. A first remanent polarization is written in the ferroelectric layer. An operating voltage is applied between the first and second electrode layers to write a second remanent polarization having a polarization value different from a polarization value of the first remanent polarization in the ferroelectric layer. An amplitude of the operating voltage varies within a voltage application time period and varies in a set voltage range.

Abstract: A ferroelectric memory device according to an embodiment of the present disclosure includes a substrate, a ferroelectric material layer disposed on the substrate, a gate electrode layer disposed on the ferroelectric material layer, and a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer.

Abstract: A ferroelectric memory device includes a substrate, an interfacial insulation layer disposed on the substrate, a recombination induction layer disposed on the interfacial insulation layer, a ferroelectric layer disposed on the recombination induction layer, and a gate electrode disposed on the ferroelectric layer.

Abstract: A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric layer and a gate electrode layer that are sequentially stacked on the substrate, and an oxygen vacancy barrier layer disposed at least between the substrate and the ferroelectric layer or between the ferroelectric layer and the gate electrode layer. The oxygen vacancy barrier layer includes a metal oxide with formula unit components that satisfy a stoichiometric ratio.

Abstract: A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.

Abstract: There is disclosed a method of manufacturing a ferroelectric memory device according to one embodiment. In the method, a substrate is prepared. An interfacial insulating layer is formed on the substrate. A ferroelectric material layer is formed on the interfacial insulating layer. An interfacial oxide layer including a first metal element is formed on the ferroelectric material layer. A gate electrode layer including a second metal element is formed on the interfacial oxide layer. The ferroelectric material layer and the interfacial oxide layer are subjected to a crystallization heat treatment to form a ferroelectric layer and a ferroelectric interfacial layer. The interfacial oxide layer reacts with the gate electrode layer so that the ferroelectric interfacial layer includes the first and second metal elements.

Abstract: A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.

Abstract: A semiconductor device includes a stack structure having a plurality of interlayer insulation layers and a plurality of gate electrode layers which are alternately stacked on a substrate, a ferroelectric insulation layer and a channel layer sequentially stacked on a sidewall of a trench that penetrates the stack structure, and a capping oxide pattern disposed between the ferroelectric insulation layer and each of the plurality of interlayer insulation layers. The capping oxide pattern and the ferroelectric insulation layer include the same metal oxide material.

Abstract: A ferroelectric memory device includes a substrate, a ferroelectric layer, a variable resistive memory layer and a gate electrode which are sequentially stacked on a surface of the substrate. The ferroelectric layer has any one of a plurality of different remanent polarization values depending on a resistive state of the variable resistive memory layer.

Abstract: In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Abstract: A ferroelectric memory device according to an embodiment includes a substrate, an interfacial insulation layer and a ferroelectric insulation layer that are sequentially disposed on an inner wall of a trench formed in the substrate. In addition, the ferroelectric memory device includes a gate electrode layer disposed on the ferroelectric insulation layer. A portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a bottom surface of the trench and a portion of the ferroelectric insulation layer disposed on the interfacial insulation layer common to a sidewall surface of the trench have crystal growth planes in directions perpendicular to the bottom surface and the sidewall surface of the trench, respectively.

Abstract: A ferroelectric memory device includes a substrate having a source region and a drain region, a first ferroelectric material layer and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the second ferroelectric material layer. The second ferroelectric material layer has an oxygen vacancy concentration different from that of the first ferroelectric material layer.

Abstract: A ferroelectric memory device according to an embodiment includes a substrate, a ferroelectric gate insulation layer disposed along an inner wall of a trench formed in the substrate, and a gate electrode layer disposed on the ferroelectric gate insulation layer. The ferroelectric gate insulation layer has a variable thickness on the inner wall of the trench.

Abstract: A ferroelectric memory device includes a substrate, a ferroelectric structure having a first ferroelectric material layer, an electrical floating layer, and a second ferroelectric material layer sequentially stacked on the substrate, and a gate electrode layer disposed on the ferroelectric structure. A hysteresis loop of the second ferroelectric material layer differs from a hysteresis loop of the first ferroelectric material layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunnel insulation layer disposed on the semiconductor substrate, a charge trap layer disposed on the tunnel insulation layer, and a control gate electrode disposed on the charge trap layer. The tunnel insulation layer includes an antiferroelectric material.

Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region, a ferroelectric structure disposed on the substrate, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.