Abstract: Provided is an ultra large-width coating device applied to a consecutive process. More particularly, the present invention relates to a coating device capable of maximizing productivity by consecutively manufacturing a large-width film without reducing physical properties of the manufactured film by overcoming a problem in that a coating width is limited during a coating process using the existing contact type coating roller, and a method for manufacturing an ultra large-width membrane using the same.

Abstract: A liquefied gas storage tank includes a corner block disposed on a corner portion, wherein the corner block includes a lower block, an upper block and an upper connecting block, the upper block includes a first inner fixing unit and a second inner fixing unit respectively provided inside a first surface and a second surface, bonded and connected to a secondary barrier, and each having a structure in which a primary inner plywood, a primary corner insulating material, and a primary outer plywood are stacked, and an inner bent portion installed at a corner spatial portion between the first inner fixing unit and the second inner fixing unit, and both side surfaces of the inner bent portion that are perpendicular to the secondary barrier each have a height reduced from a total height of each of the first and second inner fixing units.

Abstract: An electronic component includes: a multilayer capacitor including a capacitor body and a pair of external electrodes, respectively disposed on external surfaces of the capacitor body in a first direction; and an interposer disposed below the multilayer capacitor and including an interposer body, a pair of via holes penetrating through the interposer body, and a pair of via electrodes, respectively disposed in the via holes to be connected to the pair of external electrodes, respectively. 0.24T?t?0.3T, where “T” is a maximum height of the multilayer capacitor and “t” is a maximum height of the interposer.

Abstract: The liquefied gas storage tank includes a primary barrier, a primary insulation wall, a secondary barrier, and a secondary insulation wall. In a state where unit elements are arranged adjacent to each other, each of the unit elements being formed by stacking the secondary insulation wall, the secondary barrier, and a fixed insulation wall which is a part of the primary insulation wall, the primary insulation wall may comprise: a connection insulation wall provided in the space between the adjacent fixed insulation walls; first slits formed between the fixed insulation walls and the connection insulation wall when the connection insulation wall is inserted and installed between the adjacent fixed insulation walls; a plurality of second slits formed in a lengthwise direction and a widthwise direction of the fixed insulation walls; and a first insulating filler material for filling the first slits.

Abstract: A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction. A channel structure penetrates through the stack gate structure in the first direction. The channel structure makes contact with the low hand gap layer. A charge storage structure is interposed between the stack gate structure and the channel structure. The charge storage structure is configured to selectively store charge and to provide the stored charge to a memory cell, the stack gate structure, and the channel structure.

Abstract: Embodiments of the invention provide a method and device for bonding an electronic component with improved adhesive force. In accordance with at least one embodiment, the method includes preparing a printed circuit board, coating an optical alignment polymer on a bonding region of the printed circuit board, for bonding the electronic component, aligning the optical alignment polymer by irradiating the printed circuit board with UV, coating an adhesive agent on the optical alignment polymer, and mounting the electronic component on the adhesive agent.

Abstract: Disclosed herein is a printed circuit board, including: a base substrate on which a connection pad is formed; a dam spaced apart from one side of the connection pad; and a protective layer formed to surround the dam.

Abstract: There is provided a dry film resist sheet, including: a base film; a first dry film resist layer formed on the base film, the first dry film resist layer containing a binder polymer, a multi-functional monomer, and a photoinitiator; and a second dry film resist layer formed on the first dry film resist layer, the second dry film resist layer containing a binder polymer, a multi-functional monomer, a photoinitiator, and a thermal initiator.

Abstract: Disclosed herein is a method for repairing a via in which a dimple phenomenon occurs, in the case in which a dimple error occurs at the time of a process of forming the via used for electrically connecting between layers of a multi-layers circuit board. The method for repairing a via according to an exemplary embodiment of the present invention includes judging whether or not a dimple error occurs in a via; and repairing the via in which the dimple error occurs.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: Disclosed herein is a method for forming a metal wiring and an electrode using a metal nano paste, including a sintering process, wherein the sintering includes: placing a substrate on which a metal nano paste is printed in a furnace and raising a temperature of the furnace to 220 to 240° C. under a nitrogen atmosphere; heating the substrate under a mixed atmosphere of carboxylic acid and air while the temperature of the furnace is maintained at the temperature range; dropping the temperature of the furnace to 100 to 150° C. under the mixed atmosphere of carboxylic acid and air; and dropping the temperature of the furnace to room temperature under a nitrogen atmosphere. According to the present invention, a metal film having high density and a minimized amount of residual metal particles can be formed despite a low-temperature sintering process, like a case where a high-temperature sintering process is employed.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process.

Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed.

Abstract: Provided is a solar cell having a spherical surface. The solar cell includes a substrate having a back contact layer formed thereon; a plurality of carbon nanoelectrodes formed on the back contact layer so as to cross the back contact layer at right angles; a p-type junction layer formed to have a plurality of spheres which surround the plurality of carbon nanoelectrodes; an n-type junction layer and a transparent electrode layer that are sequentially laminated on the p-type junction layer; a first electrode formed on one side of the top surface of the back contact layer; and a second electrode formed on one side of the top surface of the transparent layer.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.