Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: In one aspect, a semiconductor substrate is provided having a cell area and a peripheral circuit area, and a mask layer is formed over the cell area and the peripheral circuit area of the semiconductor substrate. A FinFET gate is fabricated by forming a first opening in the mask layer to expose a first gate region in the cell area of the semiconductor substrate, and then forming a FinFET gate electrode in the first opening using a damascene process. A MOSFET gate fabricated by forming a second opening in the mask layer to expose a second gate region in the peripheral circuit area of the semiconductor substrate, and then forming a MOSFET gate electrode in the second opening using a damascene process.

Abstract: A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: Provided is a method for manufacturing a printed wiring board, which can enhance the peel strength between an insulating layer and a conductive pattern by a two-step process, that is, a semi-hardening and full-hardening of the insulating layer. In the method for manufacturing the printed wiring board having one or more layers of a conductive pattern and an insulating pattern, an insulating pattern is formed on an insulating substrate, and at least one of the insulating substrate and the insulating pattern is semi-hardened. A conductive pattern is formed on the insulating substrate and/or the insulating pattern, thereby providing a stack structure. Then, a thermal treatment is performed on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern, and the conductive pattern is fired.

Abstract: A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A conductive ink composition for inkjet printing, more particularly to a conductive ink composition for inkjet printing, which includes 30 to 85 parts by weight of metal nanoparticles, 10 to 60 parts by weight of an organic solvent, 10 to 30 parts by weight of a humectant, the humectant made of a diol or glycol base compound, and 0.1 to 10 parts by weight of an ethylene glycol-based ether compound additive for adjusting viscosity. The ink composition may be optimized, such that the viscosity of the ink may be adjusted while maintaining a high concentration of metal, when forming wiring using an inkjet device, for improved flow and ejection properties of the ink.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: Disclosed are methods of forming a printed circuit pattern and forming a guide, and a guide-forming ink. The method of forming a printed circuit pattern in accordance with the present invention includes forming a guide by using guide-forming ink having a slip property, curing the formed guide by in-situ UV, and forming a printed circuit pattern on the inside of the cured guide by using metal ink.

Abstract: In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A method of producing metal nanoparticles in a high yield rate and uniform shape and size, which is thus suitable for mass production. In addition, metal nanoparticles are provided that have superior dispersion stability when re-dispersed in various organic solvents, which thus suitable for use as a conductive ink having high conductivity. The method of producing nanoparticles includes mixing a metal precursor with a copper compound to a hydrocarbon based solvent, mixing an amine-based compound to the mixed solution of the metal precursor with copper compound and hydrocarbon based solvent, and mixing a compound including one or more atoms having at least one lone pair, selected from a group consisting of nitrogen, oxygen, sulfur and phosphorous to the mixed solution of the amine-based compound, metal precursor with a copper compound and hydrocarbon based solvent.

Abstract: A method of producing metal nanoparticles in a high yield rate and uniform shape and size, which is thus suitable for mass production. In addition, metal nanoparticles are provided that have superior dispersion stability when re-dispersed in various organic solvents, which thus suitable for use as a conductive ink having high conductivity. The method of producing nanoparticles includes mixing a metal precursor with a copper compound to a hydrocarbon based solvent, mixing an amine-based compound to the mixed solution of the metal precursor with copper compound and hydrocarbon based solvent, and mixing a compound including one or more atoms having at least one lone pair, selected from a group consisting of nitrogen, oxygen, sulfur and phosphorous to the mixed solution of the amine-based compound, metal precursor with a copper compound and hydrocarbon based solvent.

Abstract: Provided is a solar cell having a spherical surface. The solar cell includes a substrate having a back contact layer formed thereon; a plurality of carbon nanoelectrodes formed on the back contact layer so as to cross the back contact layer at right angles; a p-type junction layer formed to have a plurality of spheres which surround the plurality of carbon nanoelectrodes; an n-type junction layer and a transparent electrode layer that are sequentially laminated on the p-type junction layer; a first electrode formed on one side of the top surface of the back contact layer; and a second electrode formed on one side of the top surface of the transparent layer.

Abstract: A semiconductor package includes a semiconductor chip including a semiconductor substrate and a plurality of cell transistors arranged on the semiconductor substrate. Channel regions of the cell transistors have channel lengths that extend in a first direction, and the package further includes a supporting substrate having an upper surface on which the semiconductor chip is affixed. The supporting substrate is configured to bend in response to a temperature increase in a manner that applies a tensile stress to the channel regions of the semiconductor chip in the first direction. Related methods are also disclosed.

Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

Abstract: A method for manufacturing cover lay of printed circuit board is disclosed. With a method that includes preparing a board on which a circuit pattern is formed, and jetting a protecting ink selectively on the board by inkjet printing, a cover lay of a complicated shape may be formed easily with high accuracy and high productivity, as a polymer ink is jetted by inkjet printing to form the cover lay for a flexible circuit board.