Patents by Inventor Hye-Jung Choi

Hye-Jung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10401906
    Abstract: A cover window for a display device includes a first film; a second film on the first film; an adhesive layer between the first film and the second film; a coating layer on the second film; and an inner anti-reflective layer between the first film and the coating layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-Hoon Choi, Heon Jung Shin, Hye-Jin Oh, Jeoung Sub Lee, Bo A Kim, Sang Hoon Kim, Sang-Il Park, Hyun Joon Oh
  • Publication number: 20190222544
    Abstract: Various embodiments of the disclosure are directed to updating a selected group-based communication interface of a plurality of group-based communication interfaces with an application dialog received from an external application. User interaction data may be generated based on group-messages in group-based communication channels of the selected group-based communication interface. A validation server parses the user interaction data received to identify a triggering event associated with the external application by comparing the parsed user interaction data with a triggering event registry. The validation server then sends a trigger token to the external application associated with the triggering event. In response to receiving the trigger token, the external application sends the validation server application dialogs and/or dialog validation data that is authenticated and output for rendering to the selected group-based communication interface.
    Type: Application
    Filed: October 13, 2017
    Publication date: July 18, 2019
    Inventors: Allen James Ferrick, Edward Ishaq, Hye Jung Choi, Jason Norris, Kefan Xie, Prajna Shetty, Pranay Agarwal
  • Patent number: 10348655
    Abstract: A group-based communication platform may be utilized to execute one or more processing actions via respective external application systems based on messages exchanged among client devices via the group-based communication platform. A particular processing action may be executed for a particular message by generating a container including contextual data and payload data, wherein the payload data comprises the message for which the processing action is to be performed. The container is provided to the external application system via a proxy endpoint, thereby causing the external application system to execute the processing action based on the data included within the container.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: July 9, 2019
    Assignee: SLACK TECHNOLOGIES, INC.
    Inventors: Salman Suhail, Bruce Sullivan, Patricia Ang, Hye Jung Choi, Prajna Shetty, Andrew Fong, Michael Deng, Stephen Sowole, Tolga Akin, Pranay Agarwal
  • Patent number: 10331176
    Abstract: An electronic device includes a foldable display device, a supporting member, and a housing. The foldable display device includes at least one folding area and a plurality of non-folding areas. The supporting member is disposed in the non-folding areas to support the foldable display device. The housing includes a body part that contains the foldable display device and the supporting member, and a hinge member that folds or unfolds sections of the body part, the body part supporting the supporting member for movement relative to the housing. A folding axis defined in the folding area by the location of the hinge member is changeable in response to movement of the supporting member in the housing.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hoon Kim, Bo-A Kim, Sang-Il Park, Heon-Jung Shin, Hyun-Joon Oh, Hye-Jin Oh, Jeoung-Sub Lee, Min-Hoon Choi
  • Publication number: 20190169592
    Abstract: A gene expression cassette capable of producing psicose at high yield with high stability, a GRAS (Generally recognized as safe) microorganism, a method of producing the enzyme by using the GRAS microorganism, and a method of producing the psicose by using the GRAS microorganism and enzyme are provided.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 6, 2019
    Inventors: Jin Sol HEO, Hye Jung Kim, Min Jeong Kim, Jeong Yoon Choi, Chong Jin Park, Kang Pyo Lee
  • Publication number: 20190169591
    Abstract: A gene expression cassette capable of producing psicose at high yield with high stability, a GRAS (Generally recognized as safe) microorganism, a method of producing the enzyme by using the GRAS microorganism, and a method of producing the psicose by using the GRAS microorganism and enzyme are provided.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 6, 2019
    Inventors: Jin Sol Heo, Hye Jung Kim, Min Jeong Kim, Jeong Yoon Choi, Chong Jin Park, Kang Pyo Lee
  • Publication number: 20190169252
    Abstract: The present invention relates to a heterodimeric Fc-fused protein comprising a first Fc region and a second Fc region of an immunoglobulin Fc pair and a physiologically active protein composed of two or more different subunits, wherein one or more subunits of the physiologically active protein are linked separately to one or more ends of the N-terminus or C-terminus of the first Fc region and/or the second Fc region, and CH3 domains of the first Fc region and the second Fc region are mutated so as to promote the heterodimeric Fc formation. Moreover, the present invention relates to a pharmaceutical composition comprising the heterodimeric Fc-fused protein.
    Type: Application
    Filed: August 10, 2017
    Publication date: June 6, 2019
    Inventors: Yong Sung Kim, Keunok Jung, Ji Hee Ha, Dong Ki Choi, Hye Ji Choi, Ye Jin Kim
  • Patent number: 10309969
    Abstract: The present invention relates to a method for constructing an Fv library based on a combination of proteins, a method of screening a desired antibody using the constructed Fv library, an Fv antibody screened by the screening method, and an Fv library constructed by the Fv library construction method. The Fv library of the present invention is based on a combination of proteins so that members thereof can be individually analyzed for their function. Moreover, the Fv library enables a desired Fv antibody to be screened without needing a target antigen preparation. In addition, the protein combination based Fv library makes it possible to significantly reduce the number of protein purification processes to thereby reduce costs and time, compared to conventional DNA-based libraries.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 4, 2019
    Assignee: AbTLAS CO., LTD.
    Inventors: Byeong Doo Song, Jee Sun Yun, Song Yi Lee, Hye In Kim, Hyo Jung Choi, Jong Rip Choi
  • Publication number: 20190139207
    Abstract: An image providing method includes displaying a first image, the first image including an object and a background; receiving a user input selecting the object or the background as a region of interest; acquiring first identification information associated with the region of interest based on first attribute information of the first image; acquiring a second image from a target image, the second image including second identification information, the second identification information being the same as the first identification information; and generating an effect image based on at least one of the first image and the second image.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-sik JEONG, Hye-Sun KIM, Su-jung BAE, Seong-oh LEE, Hyeon-hee CHA, Sung-do CHOI, Hyun-soo CHOI
  • Patent number: 10115461
    Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a memory cell including a resistive memory element having a high resistance state and a low resistance state according to stored data, a selection element coupled serially to the resistive memory element, and a current clamping transistor electrically connected to a first end of the memory cell to limit an amount of a current flowing through the memory cell. In a drift recovery operation of the memory cell, a rising pulse voltage may be applied to a second end of the memory cell in a state in which the current clamping transistor has been turned off, the first end facing the second end.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 30, 2018
    Assignee: SK HYNIX INC.
    Inventors: Woo-Tae Lee, Seok-Man Hong, Tae-Hoon Kim, Sang-Hyun Ban, Hye-Jung Choi
  • Publication number: 20180182468
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.
    Type: Application
    Filed: December 26, 2017
    Publication date: June 28, 2018
    Inventors: Sang-Hyun BAN, Tae-Hoon KIM, Woo-Tae LEE, Hye-Jung CHOI
  • Patent number: 9293705
    Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 22, 2016
    Assignee: SK HYNIX INC.
    Inventors: Hye-Jung Choi, Su-Ock Chung
  • Publication number: 20160028011
    Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventors: Hye-Jung CHOI, Su-Ock CHUNG
  • Patent number: 9184378
    Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 10, 2015
    Assignee: SK HYNIX INC.
    Inventors: Hye-Jung Choi, Su-Ock Chung
  • Patent number: 8987695
    Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: SK hynix Inc.
    Inventor: Hye-Jung Choi
  • Publication number: 20140291601
    Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.
    Type: Application
    Filed: July 19, 2013
    Publication date: October 2, 2014
    Inventors: Hye-Jung CHOI, Su-Ock CHUNG
  • Publication number: 20140252299
    Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction; and a plurality of resistance variable lines interposed between the first and the second conductive lines and extending in a third direction crossing the first and the second directions.
    Type: Application
    Filed: June 21, 2013
    Publication date: September 11, 2014
    Inventors: Hye-Jung CHOI, Jun-Kyo SUH
  • Publication number: 20140077142
    Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.
    Type: Application
    Filed: January 15, 2013
    Publication date: March 20, 2014
    Applicant: SK HYNIX INC.
    Inventor: Hye-Jung CHOI
  • Publication number: 20130175496
    Abstract: A semiconductor memory device and a method for fabricating the same capable of easily controlling a contact area between a conductive line and a memory layer even at the high degree of integration. The semiconductor memory device includes a plurality of first conductive lines, a memory layer contacting with a first sidewall of each of the first conductive lines, and a plurality of second conductive lines crossing the first conductive lines and contacting with the memory layer.
    Type: Application
    Filed: August 27, 2012
    Publication date: July 11, 2013
    Inventor: Hye-Jung CHOI
  • Publication number: 20130026437
    Abstract: A method for fabricating a resistance variable memory device, includes: providing a substrate having first contacts and second contacts, where the second contacts do not overlap the first contacts; forming a line pattern over the substrate, the line pattern overlapping a first line and including a stacked structure of a first electrode, a resistor, and a second electrode; forming a first contact hole to expose the second contact; forming an insulating spacer on a sidewall of the first contact hole; forming a third contact to fill the first contact hole having the insulating spacer formed therein; and forming a third electrode over the third contact such that the third electrode overlaps a second line extending in a second direction and is cut open over the first contact, where the first and second contacts are alternately arranged on the second line.
    Type: Application
    Filed: December 28, 2011
    Publication date: January 31, 2013
    Inventors: Seok-Pyo SONG, Sung-Woong Chung, Jae-Yun Yi, Hye-Jung Choi