Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a memory cell including a resistive memory element having a high resistance state and a low resistance state according to stored data, a selection element coupled serially to the resistive memory element, and a current clamping transistor electrically connected to a first end of the memory cell to limit an amount of a current flowing through the memory cell. In a drift recovery operation of the memory cell, a rising pulse voltage may be applied to a second end of the memory cell in a state in which the current clamping transistor has been turned off, the first end facing the second end.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.

Abstract: A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction crossing the first direction; and a plurality of resistance variable lines interposed between the first and the second conductive lines and extending in a third direction crossing the first and the second directions.

Abstract: A method for fabricating a variable resistance device includes: providing a first insulating layer having a first electrode; forming a first oxide layer including a variable resistance material over the first electrode and the first insulating layer; forming a sacrifice pattern over the first oxide layer; forming a second oxide layer by reacting the first oxide layer exposed by the sacrifice pattern with oxygen; removing the sacrifice pattern; and forming a second electrode over the second oxide layer and the first oxide layer so as to be coupled to the first oxide layer.

Abstract: A semiconductor memory device and a method for fabricating the same capable of easily controlling a contact area between a conductive line and a memory layer even at the high degree of integration. The semiconductor memory device includes a plurality of first conductive lines, a memory layer contacting with a first sidewall of each of the first conductive lines, and a plurality of second conductive lines crossing the first conductive lines and contacting with the memory layer.

Abstract: A method for fabricating a resistance variable memory device, includes: providing a substrate having first contacts and second contacts, where the second contacts do not overlap the first contacts; forming a line pattern over the substrate, the line pattern overlapping a first line and including a stacked structure of a first electrode, a resistor, and a second electrode; forming a first contact hole to expose the second contact; forming an insulating spacer on a sidewall of the first contact hole; forming a third contact to fill the first contact hole having the insulating spacer formed therein; and forming a third electrode over the third contact such that the third electrode overlaps a second line extending in a second direction and is cut open over the first contact, where the first and second contacts are alternately arranged on the second line.

Abstract: An apparatus for inspecting a wafer includes a handling unit for supporting, rotating and moving the wafer in horizontal and vertical directions, a first image acquisition unit for acquiring a first image corresponding to an upper surface of the wafer supported by the handling unit, a second image acquisition unit for acquiring a second image, a third image and a fourth image corresponding to a peripheral portion of the upper surface, a side surface and a lower surface of the wafer supported by the handling unit, respectively, a first driving unit for rotating the second image acquisition unit about a peripheral portion of the wafer supported by the handling unit in order to acquiring the second, third and fourth images, and an image processing unit for inspecting defects of the wafer supported by the handling unit from the first to fourth images.

Abstract: An apparatus for inspecting a wafer includes a handling unit for supporting, rotating and moving the wafer in horizontal and vertical directions, a first image acquisition unit for acquiring a first image corresponding to an upper surface of the wafer supported by the handling unit, a second image acquisition unit for acquiring a second image, a third image and a fourth image corresponding to a peripheral portion of the upper surface, a side surface and a lower surface of the wafer supported by the handling unit, respectively, a first driving unit for rotating the second image acquisition unit about a peripheral portion of the wafer supported by the handling unit in order to acquiring the second, third and fourth images, and an image processing unit for inspecting defects of the wafer supported by the handling unit from the first to fourth images.