Abstract: The present disclosure provides a polishing pad, which may maintain polishing performances required for a polishing process, such as a removal rate and a polishing profile, minimize defects that may occur on a wafer during the polishing process, and polish layers of different materials so as to have the same level of flatness even when the layers are polished at the same time, and a method for producing the polishing pad. In addition, according to the present disclosure, it is possible to determine a polishing pad, which shows an optimal removal rate selectivity along with excellent performance in a CMP process, through the physical property values of the polishing pad without a direct polishing test.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Abstract: Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for producing the same. In the porous polyurethane polishing pad, it is possible to control the size and distribution of pores, whereby the polishing performance (i.e., polishing rate) of the polishing pad can be adjusted, by way of employing thermally expanded microcapsules as a solid phase foaming agent and an inert gas as a gas phase foaming agent.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization and a process for preparing the same. It is possible to control the size and distribution of pores in the porous polyurethane polishing pad by using thermally expanded microcapsules and an inert gas as a gas phase foaming agent, whereby the polishing performance thereof can be adjusted.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; wherein R11 and R12 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R11 and R12 is fluorine, L is a C1-C5 alkylene group or —O—, R13 and R14 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R13 and R14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Abstract: Provided are a polishing pad provided with a structural feature capable of maximizing the leakage prevention effect, the polishing pad including: a polishing layer including a first surface which is a polished surface and a second surface which is an opposite surface thereof, and including a first through hole passing through the first surface and the second surface; a window disposed in the first through hole; and a support layer disposed at the second surface of the polishing layer.

Abstract: An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Abstract: In the composition according to the embodiment, the content of an unreacted diisocyanate monomer in a urethane-based prepolymer may be controlled to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: Provided is a polishing pad that comprises a plurality of first grooves that have a shape of geometric figures that share a center; and a plurality of second grooves that radially extend from the center to the outer perimeter, wherein the depth of the second grooves is equal to, or deeper than, the depth of the first grooves. It is possible for the polishing pad to rapidly discharge any debris generated during the polishing process to reduce such defects as scratches on the surface of a wafer.

Abstract: The present invention relates to a polishing pad, a method for producing the same, and a method of fabricating a semiconductor device using the same. According to the present invention, it is possible to prevent defects from occurring due to an inorganic component contained in a polishing layer during a polishing process, by limiting the content range of the inorganic component contained in the polishing layer. In addition, an unexpanded solid foaming agent is contained in a polishing composition for producing a polishing layer and is expanded during a curing process to form a plurality of uniform pores in the polishing layer, and the content range of the inorganic component contained in the polishing layer, thereby preventing defects from occurring during the polishing process.

Abstract: The present disclosure relates to a polishing pad, a method for manufacturing the polishing pad, and a method for manufacturing a semiconductor device using the polishing pad. The polishing pad increases the area in direct contact with the semiconductor substrate during the polishing process and can prevent defects occurring on the surface of the semiconductor substrate by forming a plurality of uniform pores in the polishing layer, thereby adjusting the surface roughness characteristics of the polishing surface of the polishing layer. Further, the present disclosure may provide a method for manufacturing a semiconductor device to which the polishing pad is applied.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Abstract: The present disclosure provides a polishing pad, which may maintain polishing performances required for a polishing process, such as a removal rate and a polishing profile, minimize defects that may occur on a wafer during the polishing process, and polish layers of different materials so as to have the same level of flatness even when the layers are polished at the same time, and a method for producing the polishing pad. In addition, according to the present disclosure, it is possible to determine a polishing pad, which shows an optimal removal rate selectivity along with excellent performance in a CMP process, through the physical property values of the polishing pad without a direct polishing test.

Abstract: An embodiment relates to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. In the porous polyurethane polishing pad, the polishing performance (or polishing rate) thereof can be controlled by adjusting the size and distribution of pores in the polishing pad.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Abstract: The present disclosure relates to a polishing pad, a method of manufacturing the polishing pad, and a method of manufacturing a semiconductor device using the same. In the polishing pad, an unexpanded solid-phase blowing agent is included in a polishing composition when a polishing layer is manufactured, and the unexpanded solid-phase blowing agent is expanded during a curing process to form a plurality of uniform pores in the polishing layer, such that defects occurring on a surface of the semiconductor substrate may be prevented. In addition, the present disclosure may provide a method of manufacturing a semiconductor device to which the polishing pad is applied.

Abstract: In the composition according to the embodiment, the composition of oligomers that constitute the chains in a urethane-based prepolymer may be adjusted to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.