Abstract: Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.

Abstract: In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization and a process for preparing the same. It is possible to control the size and distribution of pores in the porous polyurethane polishing pad by using thermally expanded microcapsules and an inert gas as a gas phase foaming agent, whereby the polishing performance thereof can be adjusted.

Abstract: The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Abstract: Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes in its main chain a silane repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is about 40 or less wherein R11 and R12 are each independently hydrogen or C1-C10 alkyl groups, and n is an integer from 1 to 30.

Abstract: A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; wherein R11 and R12 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R11 and R12 is fluorine, L is a C1-C5 alkylene group or —O—, R13 and R14 are each independently selected from the group consisting of hydrogen, C1-C10 alkyl groups, and fluorine, with the proviso that at least one of R13 and R14 is fluorine, and n and m are each independently an integer from 0 to 20, with the proviso that n and m are not simultaneously 0.

Abstract: In the composition according to an embodiment, the weight ratio of toluene 2,4-diisocyanate in which one NCO group is reacted and unreacted toluene 2,6-diisocyanate in the urethane-based prepolymer is adjusted, whereby such physical properties as gelation time can be controlled. Thus, the polishing rate and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled while it has a hardness suitable for a soft pad, whereby it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: The present invention provides a polishing pad whose crosslinking density is adjusted to enhance the performance of the CMP process such as polishing rate and cut pad rate, in addition, in the process for preparing a polishing pad according to the embodiment, it is possible to implement such a crosslinking density by a simple method of controlling the preheating temperature of the mold for curing, Thus, the polishing pad may be applied to a process of preparing a semiconductor device, which comprises a CMP process, to provide a semiconductor device such as a wafer of excellent quality.

Abstract: The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Abstract: In the composition according to the embodiment, the content of an unreacted diisocyanate monomer in a urethane-based prepolymer may be controlled to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: In the composition according to the embodiment, the composition of oligomers that constitute the chains in a urethane-based prepolymer may be adjusted to control the physical properties thereof such as gelation time. Thus, since the micropore characteristics, polishing rate, and pad cut rate of a polishing pad obtained by curing the composition according to the embodiment may be controlled, it is possible to efficiently manufacture high-quality semiconductor devices using the polishing pad.

Abstract: Provided is a polishing pad that comprises a plurality of first grooves that have a shape of geometric figures that share a center; and a plurality of second grooves that radially extend from the center to the outer perimeter, wherein the depth of the second grooves is equal to, or deeper than, the depth of the first grooves. It is possible for the polishing pad to rapidly discharge any debris generated during the polishing process to reduce such defects as scratches on the surface of a wafer.

Abstract: An embodiment relates to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. In the porous polyurethane polishing pad, the polishing performance (or polishing rate) thereof can be controlled by adjusting the size and distribution of pores in the polishing pad.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Abstract: Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Abstract: Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.

Abstract: Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for producing the same. In the porous polyurethane polishing pad, it is possible to control the size and distribution of pores, whereby the polishing performance (i.e., polishing rate) of the polishing pad can be adjusted, by way of employing thermally expanded microcapsules as a solid phase foaming agent and an inert gas as a gas phase foaming agent.