Abstract: A liquid crystal display device including a first substrate, a common electrode formed over the first substrate, and a second substrate disposed opposite the first substrate. A common voltage-applying member applies a common voltage to the common electrode and maintains a cell gap between the first substrate and the second substrate. The common voltage-applying member includes an insulator and a conductor formed over the insulator.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract: In a thin film transistor substrate, a method of manufacturing the same, and a display apparatus having the same, a thin film transistor, a gate member, and a storage member are formed on an insulating substrate. The gate member has a gate line and a gate electrode electrically connected to the gate line, and the storage member has a storage line, a first storage electrode, and a second storage electrode. A data member is formed on an active layer. The data member includes a data line crossing the gate line, a third storage electrode overlapped with the first storage electrode and a fourth storage electrode overlapped with the second storage electrode. Thus, a capacitance variation of a storage capacitor may be prevented, thereby improving display quality of a display apparatus.

Abstract: In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge, placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: A display substrate includes a TFT layer, a passivation layer, an organic layer, an inorganic insulating layer and a pixel electrode. The TFT layer includes gate and data lines, a thin film transistor and a storage electrode. The data line crosses the gate line, and is electrically insulated from the gate line by a gate insulating layer. The TFT is electrically connected to the gate and data lines. The passivation layer covers the TFT layer. The organic layer is on the passivation layer. The inorganic insulating layer of a low temperature deposition is on the organic layer, and the low temperature is about 100° C. to about 250° C. The pixel electrode is on the inorganic insulating layer to be electrically connected to the TFT through a contact hole that is formed through the inorganic insulating layer, the organic layer and the passivation layer. The inorganic insulating layer helps to block leakage of impurities from the organic layer to layers above the inorganic insulating layer.

Abstract: In a thin film transistor substrate, a method of manufacturing the same, and a display apparatus having the same, a thin film transistor, a gate member, and a storage member are formed on an insulating substrate. The gate member has a gate line and a gate electrode electrically connected to the gate line, and the storage member has a storage line, a first storage electrode, and a second storage electrode. A data member is formed on an active layer. The data member includes a data line crossing the gate line, a third storage electrode overlapped with the first storage electrode and a fourth storage electrode overlapped with the second storage electrode. Thus, a capacitance variation of a storage capacitor may be prevented, thereby improving display quality of a display apparatus.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: A liquid crystal display device including a first substrate, a common electode formed over the first substrate, and a second substrate disposed opposite the first substrate. A common voltage-applying member applies a common voltage to the common electrode and maintains a cell gap between the first substrate and the second substrate. The common voltage-applying member includes an insulator and a conductor formed over the insulator.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract: Provided are a method of manufacturing a liquid crystal display including an amorphous silicon thin film transistor, a liquid crystal display, and an aging system adapted to the method of manufacturing the liquid crystal display.

Abstract: In a thin film transistor substrate, a method of manufacturing the same, and a display apparatus having the same, a thin film transistor, a gate member, and a storage member are formed on an insulating substrate. The gate member has a gate line and a gate electrode electrically connected to the gate line, and the storage member has a storage line, a first storage electrode, and a second storage electrode. A data member is formed on an active layer. The data member includes a data line crossing the gate line, a third storage electrode overlapped with the first storage electrode and a fourth storage electrode overlapped with the second storage electrode. Thus, a capacitance variation of a storage capacitor may be prevented, thereby improving display quality of a display apparatus.

Abstract: A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode.

Abstract: A thin film transistor array panel comprising: an insulating substrate; a plurality of gate lines formed on the insulating substrate and including a plurality of gate electrodes and end portions; a plurality of storage electrode lines formed on the insulating substrate; a gate insulating layer formed on the gate lines and storage electrode lines; a semiconductor layer formed on the gate insulating layer; a ohmic contact layer formed on the semiconductor layer; a plurality of data lines formed on the gate insulating layer, intersecting the gate lines to define a display area, and having source electrodes and end portions; a plurality of drain electrodes facing the source electrodes; a passivation layer formed on the data lines and drain electrodes and having contact holes; a plurality of pixel electrodes formed on the passivation layer and connected to the drain electrodes through the contact holes; a storage line connecting bar connecting the storage electrode lines; and a redundant connecting line connecting

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.

Abstract: A liquid crystal display device including a first substrate, a common electrode formed over the first substrate, and a second substrate disposed opposite the first substrate. A common voltage-applying member applies a common voltage to the common electrode and maintains a cell gap between the first substrate and the second substrate. The common voltage-applying member includes an insulator and a conductor formed over the insulator.