Patents by Inventor Hyeng Ouk Lee
Hyeng Ouk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9100029Abstract: Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.Type: GrantFiled: February 10, 2014Date of Patent: August 4, 2015Assignee: SK Hynix IncInventors: Hyeng Ouk Lee, Sang Kwon Lee
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Publication number: 20150213861Abstract: The semiconductor device includes a first data aligner, an input strobe signal generator and a second data aligner. The first data aligner aligns input data in synchronization with an internal strobe signal to generate alignment data. The input strobe signal generator generates first and second delay signals from the internal strobe signal. The input strobe signal generator also latches an input clock signal generated from an external clock signal after a write latency period from a period when a write operation commences, in response to the first and second delay signals to generate an input strobe signal. The second data aligner re-aligns the alignment data in synchronization with the input strobe signal to generate internal data.Type: ApplicationFiled: June 11, 2014Publication date: July 30, 2015Inventors: Hyeng Ouk LEE, Keun Soo SONG
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Publication number: 20150123826Abstract: Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.Type: ApplicationFiled: February 10, 2014Publication date: May 7, 2015Applicant: SK hynix Inc.Inventors: Hyeng Ouk LEE, Sang Kwon LEE
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Publication number: 20140344654Abstract: A semiconductor system including a semiconductor circuit configured to compare a first error detection code generated by performing an operation on read data to a second error detection code and determine a data transmission error, and a controller configured to provide the second error detection code, generated by performing an operation on expect data based on the read data, to the semiconductor circuit.Type: ApplicationFiled: September 6, 2013Publication date: November 20, 2014Applicant: SK hynix Inc.Inventor: Hyeng Ouk LEE
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Patent number: 8422331Abstract: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.Type: GrantFiled: January 31, 2011Date of Patent: April 16, 2013Assignee: Hynix Semiconductor Inc.Inventor: Hyeng Ouk Lee
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Patent number: 8351282Abstract: A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.Type: GrantFiled: December 16, 2010Date of Patent: January 8, 2013Assignee: SK Hynix Inc.Inventor: Hyeng Ouk Lee
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Patent number: 8295100Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.Type: GrantFiled: May 13, 2010Date of Patent: October 23, 2012Assignee: Hynix Semiconductor Inc.Inventor: Hyeng-Ouk Lee
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Publication number: 20120106274Abstract: A semiconductor memory apparatus includes a data input enable signal generation block configured to sequentially delay a data strobe signal to generate a first delayed data strobe signal, a second delayed data strobe signal, a third delayed data strobe signal and a fourth delayed data strobe signal, and generate a data strobe enable signal in response to a CAS write signal, a CAS write latency signal and the first to fourth delayed data strobe signals, a latch control signal generation block configured to output the data strobe signal as a latch control signal during an enable period of the data strobe enable signal, and a data latch block configured to latch data in response to the latch control signal and output latched data.Type: ApplicationFiled: December 16, 2010Publication date: May 3, 2012Applicant: Hynix Semiconductor Inc.Inventor: Hyeng Ouk LEE
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Patent number: 8139429Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.Type: GrantFiled: December 16, 2010Date of Patent: March 20, 2012Assignee: Hynix Semiconductor Inc.Inventor: Hyeng Ouk Lee
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Publication number: 20110211397Abstract: A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.Type: ApplicationFiled: May 13, 2010Publication date: September 1, 2011Inventor: Hyeng-Ouk Lee
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Publication number: 20110175654Abstract: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.Type: ApplicationFiled: January 31, 2011Publication date: July 21, 2011Inventor: Hyeng Ouk LEE
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Publication number: 20110085395Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Applicant: HYNIX SEMICONDUCTOR, INC.Inventor: Hyeng Ouk Lee
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Patent number: 7911251Abstract: A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.Type: GrantFiled: June 30, 2009Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Hyeng Ouk Lee, Kwan Weon Kim
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Patent number: 7869288Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.Type: GrantFiled: July 29, 2008Date of Patent: January 11, 2011Assignee: Hynix Semiconductor Inc.Inventor: Hyeng-Ouk Lee
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Publication number: 20100283519Abstract: A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.Type: ApplicationFiled: June 30, 2009Publication date: November 11, 2010Inventors: Hyeng Ouk LEE, Kwan Weon KIM
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Patent number: 7616034Abstract: Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a frequency of the external clock in response to the control signal, a decoder for outputting a selection signal by decoding the detection signal, and a delay unit for outputting a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal.Type: GrantFiled: June 29, 2007Date of Patent: November 10, 2009Assignee: Hynix Semiconductor Inc.Inventor: Hyeng Ouk Lee
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Publication number: 20090040847Abstract: An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information and to generate an output control signal having enable timing according to a DLL on/off mode, and an output enable signal output unit configured to receive the output control signal and to output an output enable signal in response to a read command and a DLL clock signal.Type: ApplicationFiled: July 29, 2008Publication date: February 12, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventor: Hyeng Ouk Lee
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Publication number: 20080080267Abstract: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.Type: ApplicationFiled: March 8, 2007Publication date: April 3, 2008Inventor: Hyeng Ouk LEE
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Publication number: 20080008283Abstract: Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a frequency of the external clock in response to the control signal, a decoder for outputting a selection signal by decoding the detection signal, and a delay unit for outputting a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal.Type: ApplicationFiled: June 29, 2007Publication date: January 10, 2008Inventor: Hyeng Ouk LEE