Abstract: Disclosed is a printed circuit board (PCB) structure, in which an electromagnetic signal transmitting antenna and/or an electromagnetic signal receiving antenna, and an electromagnetic signal transferring tunnel (EM-tunnel) are embedded, the PCB structure including a PCB, an EM-tunnel that includes a dielectric core and a metal clad that surrounds the dielectric core and that is embedded in the PCB to be parallel to the PCB, and at least one transmitting antenna and/or at least one receiving antenna that are embedded in the PCB, wherein the transmitting antenna and/or the receiving antenna are arranged at an input port and an output port of the EM-tunnel embedded in the PCB to transmit and receive electromagnetic signals to and from the interior of the EM-tunnel.

Abstract: Disclosed is a chip-to-chip interface using a microstrip circuit and a dielectric waveguide. A board-to-board interconnection device, according to one embodiment of the present invention, comprises: a waveguide which has a metal cladding and transmits a signal from a transmitter-side board to a receiver-side board; and a microstrip circuit which is connected to the waveguide and has a microstrip-to-waveguide transition (MWT), wherein the microstrip circuit matches a microstrip line and the waveguide, adjusts the bandwidth of a predetermined first frequency band among the frequency bands of the signal, and provides same to the receiver.

Abstract: Disclosed are an optical spectroscopy system using a pipeline-structured matched filter and a dual-slope analog digital converter, and a method for controlling the optical spectroscopy system. The optical spectroscopy system may comprise: a pipeline-structured matched filter sequentially connecting input voltage, transmitted by means of an amplifier, to a first capacitor and a second capacitor by means of a first switch terminal; and a dual-slope analog digital converter for sequentially receiving, by means of a second switch terminal, the electric charge stored in the first capacitor and second capacitor, and digitizing the input voltage.

Abstract: Disclosed are a time division spread spectrum code-based optical spectroscopy system capable of controlling irradiation power and a method for controlling the optical spectroscopy system. The optical spectroscopy system may comprise: a light transmission unit for irradiating light to a particular region of a subject by means of a light source, wherein the light is irradiated so that the overall energy is consistently maintained by reducing the light irradiation time and increasing the strength of the light; and a light receiving unit for collecting emergent light which has passed through the particular region.

Abstract: Disclosed are an apparatus and a method for removing strands of hair from a near-infrared spectroscopy. The apparatus for removing strands of hair from a near-infrared spectroscopy may comprise: an arch-shaped main body worn on the head of a user, having a plurality of protrusions formed at an inner side part of the arch-shaped main body, and configured to expose a portion of scalp by arranging the strands of hair; a probe configured to come into close contact with the scalp; and a sensor configured to be accommodated inside the probe and receive light.

Abstract: Disclosed are a mobile and expandable firmware-based optical spectroscopy system and a method for controlling same. The optical spectroscopy system may comprise: a wearing part attached to a particular region of a subject to irradiate light, on the basis of a firmware, to the particular region and measure the bodily signals of the subject by collecting emergent light which has passed through the particular region; and a monitoring unit, connected to the wearing part via a wired or wireless network, for controlling the strength of the light irradiated from the wearing part.

Abstract: Disclosed are an optical spectroscopy system using a matched filter-based broadband signal receiver for stable data extraction, and a method for controlling the optical spectroscopy system. The optical spectroscopy system may comprise: a light transmission unit for irradiating light on a particular region of a subject by means of a plurality of light sources, wherein the light irradiated from the plurality of light sources is code-modulated by means of the Walsh codes and then irradiated; and a light receiving unit for detecting emergent light which has passed through the particular region, wherein the light source is identified by demodulating the light by means of the Walsh codes.

Abstract: The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

Abstract: Disclosed is a printed-circuit board (PCB) structure having an electromagnetic-tunnel-embedded architecture, the PCB structure including a PCB, and an EM-tunnel-embedded in the PCB, wherein the EM-tunnel includes a dielectric core and a metal clad which surrounds the dielectric core and has at least one port exposed to a surface of the PCB.

Abstract: The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.

Abstract: The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract: An exemplary embodiment of the present invention provides an improved dielectric waveguide named electrical fiber. The electrical fiber with a metal cladding may isolate the interference of the signals in other wireless channels and adjacent electrical fibers, which typically causes band-limitation problem, for a smaller radiation loss and better signal guiding to lower the total transceiver power consumption as the transmit distance increases. Also, the electrical fiber may have frequency independent attenuation characteristics to enable high data rate transfer with little or even without any additional receiver-side compensation due to vertical coupling of the electrical fiber and an interconnection device.

Abstract: An efficient method for the extraction of hemodynamic responses in Near-Infrared Spectroscopy (NIRS) systems is proposed to increase the spatial and temporal resolution without hardware overhead. The performance improvement is attributed to high Signal-to-Noise-Ratio (SNR) receivers, a modulation scheme, and a Multi-Input-Multi-Output (MIMO) based data extraction algorithm. The proposed system shows an over 2× increment in the figure of merit (FOM) compared to conventional designs. Experimental results support the validity of the proposed system.

Abstract: A variable-precision distributed arithmetic (VPDA) multi-input multi-output (MIMO) equalizer is presented to reduce the size and dynamic power of 112 Gbps dual-polarization quadrature phase-shift-keying (DP-QPSK) coherent optical communication receivers. The VPDA MIMO equalizer compensates for channel dispersion as well as various non-idealities of a time-interleaved successive approximation register (SAR) based analog-to-digital converter (ADC) simultaneously by using a least mean square (LMS) algorithm. As a result, area-hungry analog domain calibration circuits are not required. In addition, the VPDA MIMO equalizer achieves 45% dynamic power reduction over conventional finite impulse response (FIR) equalizers by utilizing the minimum required resolution for the equalization of each dispersed symbol.

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.