Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.

Abstract: An example method includes receiving a phase correction signal representing a phase difference between a source signal and a reference signal, generating a first control voltage from the phase correction signal using a charge pump circuit, generating a second control voltage from the phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for an offset error present in the first control voltage, calculating a VCO control signal based on a linear combination of the first and the second control voltages; and generating the source signal in response to the VCO control signal.

Abstract: Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal.

Abstract: A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.

Abstract: A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.

Abstract: An example method includes receiving a phase correction signal representing a phase difference between a source signal and a reference signal, generating a first control voltage from the phase correction signal using a charge pump circuit, generating a second control voltage from the phase correction signal in response to a digitally filtered version of the phase correction signal, wherein the second control voltage corrects for an offset error present in the first control voltage, calculating a VCO control signal based on a linear combination of the first and the second control voltages; and generating the source signal in response to the VCO control signal.

Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Abstract: A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase correction signals are only generated if a predetermined data sample pattern is observed. In particular, the predetermined data sample pattern is preferably a transition from one to zero. Thus, transitions from zero to one will not provide a valid phase update output signal, even though a transition has occurred. In other embodiments the predetermined data sample pattern is preferably a one to zero transition preceded by an additional logic one sample.

Abstract: An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.

Abstract: Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.

Abstract: An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.

Abstract: A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwith (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.

Abstract: A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.

Abstract: A noise tolerant voltage controlled oscillator is described. The voltage controlled oscillator include a varactor element as part of an LC tank circuit. The varactor element is biased by a bias signal and a bias-dependent control signal. The bias-dependent control signal tunes the LC tank circuit. Because the control signal is bias-dependent, noise and other deleterious influences do not cause the varactor element to deviate in capacitance. Instead, the bias-dependent control signal is a tuning signal that is centered around the bias signal, which allows the varactor element to provide a constant capacitance in the event of a varying bias signal.