Abstract: For determining a failure characteristic of a semiconductor device, a leakage current characteristic is measured for the semiconductor device to determine a plurality of stress bias zones. A respective set of parameters that define a respective failure characteristic of the semiconductor device is determined for each of the stress bias zones such that the failure characteristic is accurately determined for a wide range of operating voltages.

Abstract: A semiconductor component having a monitoring structure suitable for monitoring metal migration of a metallization system and a method for manufacturing the semiconductor component. A semiconductor substrate is provided having a major surface. A first extrusion monitoring element is formed over the major surface. A notched test element is formed over the first extrusion monitoring element. A second extrusion monitoring element is formed over the notched test element. A current is conducted through the notched test element. The resistance between the notched test element and at least one of the first and second extrusion monitoring elements is monitored to determine if a short has been created.

Abstract: A space-saving test structure includes a core metal line, at least one extrusion detection line and an extrusion monitoring segment. The core metal line has a “non-linear configuration” and is capable of conducting current for an electromigration test, an isothermal test, and extrusion monitoring. The at least one extrusion detection line is situated adjacent to the core metal line. The extrusion monitoring segment is electrically connected to the at least one extrusion detection line. The extrusion monitoring segment is adapted to determine whether an extrusion occurs in the core metal line by measuring a resistance between the core metal line and the at least one extrusion detection line.

Abstract: According to one exemplary embodiment, a test structure for determining electromigration and interlayer dielectric failure comprises a first metal line situated in a metal layer of the test structure. The test structure further comprises a second metal line situated adjacent and substantially parallel to the first metal line, where the second metal line is separated from the first metal line by a first distance, and where the first distance is substantially equal to minimum design rule separation distance. The test structure further comprises an interlayer dielectric layer situated between the first metal line and the second metal line. According to this exemplary embodiment, electromigration failure is determined when a first resistance of the first metal line or a second resistance of the second metal line is greater than a predetermined resistance, and interlayer dielectric failure is determined when a first current is detected between the first and second metal lines.

Abstract: A method of predicting a lifetime of a semiconductor device at a predetermined operating condition includes performing a hot carrier injection (HCI) accelerated stress test on a plurality of MOS transistors. For each HCI test, a HCI lifetime and a maximum substrate or gate current are determined. The HCI test data is fit with a hot carrier lifetime model and fitting parameters are obtained. A wafer level test is performed on at least 10N transistors in which a maximum substrate or gate current is determined for each transistor. A median lifetime to failure is determined for the statistical distribution of maximum substrate or gate current values at the predetermined operating condition. From the determined median lifetime to failure, a projected lifetime at a fractional cumulative failure is calculated.

Abstract: According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.

Abstract: A method of generating an operating condition projection corresponding to a predetermined lifetime for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition by inducing a predetermined drain-source voltage for each stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Abstract: According to one exemplary embodiment, a method for determining a Weibull slope at a specified temperature utilizing a test structure comprises a step of performing a number of groups of failure tests on the test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test temperatures, and where each group of failure tests corresponds to a respective group of test data. The method further comprises utilizing the number of groups of test data to determine a scaling line. The method further comprises determining a scaling factor at the specified temperature utilizing the scaling line. The method further comprises utilizing the scaling factor to determine the Weibull slope. The method may further comprise utilizing the Weibull slope to determine a lifetime of the semiconductor die.

Abstract: A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Abstract: A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode, at least one of sidewall/spacers, second sidewalls or a barrier layer, in which the floating gate is positioned above the channel region. The floating gate may be separated from the channel region by one or more of a reverse tunnel dielectric layer, the barrier layer and a pad dielectric layer. The floating gate may be a metal floating gate.

Abstract: A space-saving test structure includes a core metal line, at least one extrusion detection line and an extrusion monitoring segment. The core metal line has a “non-linear configuration” and is capable of conducting current for an electromigration test, an isothermal test, and extrusion monitoring. The at least one extrusion detection line is situated adjacent to the core metal line. The extrusion monitoring segment is electrically connected to the at least one extrusion detection line. The extrusion monitoring segment is adapted to determine whether an extrusion occurs in the core metal line by measuring a resistance between the core metal line and the at least one extrusion detection line.

Abstract: According to one exemplary embodiment, a method for determining a Weibull slope at a specified bias voltage comprises a step of performing a number of groups of failure tests on a test structure to determine a number of groups of test data, where each of the groups of failure tests is performed at a respective one of a number of test bias voltages, and where each group of failure tests corresponds to a respective group of test data. The test structure may be an array of MOS transistors, for example. The method further comprises utilizing the number of groups of test data to determine a scaling line. According to this exemplary embodiment, the method further comprises utilizing the scaling line to determine the Weibull slope at the specified bias voltage. The method may further comprise utilizing the Weibull slope to determine a lifetime of a semiconductor die.

Abstract: An interconnect structure which has improved stress migration reliability is disclosed. According to one exemplary embodiment, the interconnect structure comprises a top interconnect metal layer, at least one via and a bottom interconnect metal layer. The bottom interconnect metal layer comprises at least one finger. The at least one via electrically connects the top interconnect metal layer to the at least one finger. The finger width of the at least one finger is less than a bottom layer width of the bottom interconnect metal layer. In another embodiment, a method for fabricating the above interconnect structure is disclosed.

Abstract: One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

Abstract: In accordance with the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlaying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the gate and the source/drain regions are silicon germanium.

Abstract: A method and system for determining an operating voltage for a semiconductor device. A first plurality of lifetimes may be determined for a first plurality of semiconductor device where the polysilicon lines in each of the first plurality of semiconductor devices have the same total area but different peripheral lengths. A second plurality of lifetimes may be determined for a second plurality of semiconductor devices where the polysilicon lines in each of the second semiconductor device have the same peripheral length but different total areas. Further, the STI structures (used to separate one or more active areas) in each of the second plurality of semiconductor devices may have the same length as the STI structures (used to separate one or more active areas) in each of the first plurality of semiconductor devices. The operating voltage may be determined based on the first and second plurality of lifetimes.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin.

Abstract: For fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, any region of a stack of a layer of tunnel dielectric material, a layer of floating gate material, a layer of floating dielectric material, and a layer of control gate material, not under a patterning structure, is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material over the tunnel dielectric structure, to form a floating dielectric structure comprised of the floating dielectric material disposed over the floating gate structure, and to form a control gate structure comprised of the control gate material disposed over the floating dielectric structure.

Abstract: A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.