Abstract: A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes a first edge, a second edge and a base. The method and system further include providing a source and/or a drain for the at least one gate. The source and/or a drain are in proximity to the first edge or the first and second edges of the at least one gate. The at least one gate, the source and/or drain or both the at least one gate and the source and/or drain are configured such that source and/or drain do not substantially overlap the at least one gate at the base of the at least one gate.

Abstract: A method of memory device fabrication. In one embodiment, the method of memory device (400) fabrication comprises implanting an element (200) in a substrate (440). The element (200) causes an inherent elongational realignment of atoms in silicon (101,102) when silicon (100) is formed (471) upon the substrate (440) with the element (200) implanted therein. A layer of silicon (100) is formed (471) on the substrate having the element (200) implanted therein (470), wherein alignment of atoms (101) of the silicon elongates (102) to an atomical alignment equivalent (101g) to said element (200). The layer of silicon (471) and the substrate (470) are crystallized subsequent to the elongational realignment of atoms of the layer of silicon (101g), wherein a crystallized layer of elongated silicon (101g) decreases electron scattering thus realizing increase core gain in the memory device (400).

Abstract: A method for reducing off-state leakage current of a MOSFET while promoting the formation of an epitaxial gate insulator layer between the substrate and gate stack includes implanting source/drain dopant into the substrate, and then forming a very thin epitaxial Silicon layer on the substrate by, e.g., molecular beam epitaxy. The high-k gate insulator layer is then deposited on the epitaxial layer, without an interfering native oxide or interfacial oxide being formed between the insulator layer and substrate, while establishing a very steep retrograde dopant profile and hence reducing off-state leakage current through the channel region.

Abstract: The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mobility.

Abstract: A method and system for qualifying an oxide-nitride-oxide (QNO) layer including a first oxide layer, a nitride layer and a control oxide layer in a semiconductor device is disclosed. The method and system including determining a first plurality of dielectric breakdown voltages and a first plurality of lifetimes and determining a second plurality of dielectric voltages and a second plurality of lifetimes. The first plurality of dielectric breakdown voltages and lifetimes being determined utilizing a plurality of ramp rates for a first plurality of ONO layers having a particular nitride layer thickness and a plurality of control oxide layer thicknesses. The second plurality of dielectric breakdown voltages and lifetimes layer being determined utilizing the plurality of ramp rates for each of a second plurality of ONO layers having a particular control oxide layer thickness and a plurality of nitride layer thicknesses.

Abstract: A method for forming a high voltage gate oxide having a high quality and reliability for use with non-volatile memory devices is provided. Field oxide isolation regions are formed in the top surface of a semiconductor substrate so as to define a first active region, a second active region, and a third active region. A sacrificial oxide layer is formed on the top surface of the semiconductor layer and overlying the first through third active regions. The sacrificial oxide layer is removed from only the first active region. A tunnel oxide layer is formed over the first active region and over the sacrificial oxide layer overlying the second active region and the third active region. A floating gate structure is formed in the first active region. The tunnel oxide layer and the sacrificial oxide layer over the respective second active region and third active region are removed subsequent to forming the floating gate structure.

Abstract: A method and system for providing a Flash memory device is disclosed. The Flash memory device includes a core and a periphery. The method and system include providing the core for the Flash memory device and providing a plurality of isolation structures. A portion of the plurality of isolation structures is for isolating a plurality of devices at the periphery of the Flash memory device. Each of the plurality of isolation structures includes a corner and an oxide filler. The method and system further include providing the plurality of isolation structures by processing the plurality of isolation structures to reduce thinning of the oxide filler in proximity to the corner of the isolation structure.

Abstract: A method and system for qualifying an oxide-nitride-oxide (ONO) layer including a first oxide layer, a nitride layer and a control oxide layer in a semiconductor device is disclosed. The method and system include determining the lifetime of the ONO layer using the activation energy of the ONO layer and the field acceleration factor of the ONO layer. The activation energy and field acceleration factor of the ONO layer are determined by testing a plurality of ONO layers, some of which have a particular nitride layer thickness and varying control oxide layer thicknesses and others which have a particular control oxide layer thicknesses and varying nitride layer thicknesses. The plurality of ONO layers is tested using a variety of applied voltages to obtain lifetimes for the plurality of ONO layers. Based on these lifetimes and voltages, the activation energy and field acceleration factor for the ONO layer can be obtained.

Abstract: A method and system for determining an operating voltage for a semiconductor device is disclosed. The semiconductor device includes at least one silicon trench isolation (STI) structure and at least one active area. The method and system include determining a first plurality of lifetimes and a second plurality of lifetimes. The first plurality of lifetimes is determined for a first plurality of semiconductor devices having a first plurality of STI structures. The first plurality of semiconductor devices have a particular area of STI structures and a plurality of peripheral length of STI structures. The second plurality of lifetimes is determined for a second plurality of semiconductor devices having a second plurality of STI structures. The second plurality of semiconductor devices have a plurality of areas of STI structures and a particular peripheral length of STI structures.

Abstract: In accordance with the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlaying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the gate and the source/drain regions are silicon germanium.

Abstract: For fabricating a flash memory cell, a dummy gate structure is formed on an active device area of a semiconductor substrate. A drain bit line junction is formed within the active device area of the semiconductor substrate to a first side of the dummy gate structure, and a source bit line junction is formed within the active device area of the semiconductor substrate to a second side of the dummy gate structure. A drain bit line silicide is formed within the drain bit line junction, and a source bit line silicide is formed within the source bit line junction. Furthermore, an interlevel material is formed to surround the dummy gate structure, and the dummy gate structure is then etched away to form a gate opening within the interlevel material. Spacers are then formed at sidewalls of the gate opening within the gate opening.

Abstract: A method and system for providing a Flash memory device is disclosed. The Flash memory device includes a core and a periphery. The method and system include providing the core for the Flash memory device and providing a plurality of isolation structures. A portion of the plurality of isolation structures is for isolating a plurality of devices at the periphery of the Flash memory device. Each of the plurality of isolation structures includes a corner and an oxide filler. The method and system further include providing the plurality of isolation structures by processing the plurality of isolation structures to reduce thinning of the oxide filler in proximity to the corner of the isolation structure.

Abstract: This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench-trench short circuiting.

Abstract: A method for forming a high voltage gate oxide having a high quality and reliability for use with nonvolatile memory devices is provided. Field oxide isolation regions are formed in the top surface of a semiconductor substrate so as to define a first active region, a second active region, and a third active region. A sacrificial oxide layer is formed on the top surface of the semiconductor layer and overlying the first through third active regions. The sacrificial oxide layer is removed from only the first active region. A tunnel oxide layer is formed over the first active region and over the sacrificial oxide layer overlying the second active region and the third active region. A floating gate structure is formed in the first active region. The tunnel oxide layer and the sacrificial oxide layer over the respective second active region and third active region are removed subsequent to forming the floating gate structure.

Abstract: Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high, dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material.

Abstract: For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant, such as boron for example, is implanted into a first region of the layer of gate electrode material disposed over a first active device area of the semiconductor substrate. The first region of the layer of gate electrode material is patterned to form a PMOS gate electrode. The layer of gate dielectric material is patterned to form a PMOS gate dielectric disposed under the PMOS gate electrode.

Abstract: For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a PMOS gate dielectric is formed on the semiconductor substrate, and a PMOS dummy gate electrode is formed on the gate dielectric. A P-type dopant is implanted into exposed regions of the semiconductor substrate to form a PMOS drain junction and a PMOS source junction. A thermal anneal is performed to activate the drain and source P-type dopant within the drain and source junctions. A PMOS drain silicide is formed with the drain junction, and a PMOS source silicide is formed with the source junction, in a silicidation process. An insulating material is deposited to surround the dummy gate electrode and the gate dielectric. The dummy gate electrode is etched away to form a PMOS gate electrode opening surrounded by the insulating material.

Abstract: The present invention is a method for fabricating high quality oxides on a plurality of semiconductor wafers by proper positioning of those semiconductor wafers with respect to each other within a wafer cassette for processing within a bath. Each of the plurality of semiconductor wafers has a predetermined diameter. The method of the present invention includes a step of placing the plurality of semiconductor wafers in a wafer cassette that holds the plurality of semiconductor wafers in a stack configuration. According to the present invention, the plurality of semiconductor wafers within the wafer cassette are spaced with a respective predetermined distance between any two adjacent semiconductor wafers such that a respective ratio of the respective predetermined distance to the predetermined diameter of a semiconductor wafer is at least 0.12.

Abstract: Methods of manufacturing insulating materials and semiconductor devices incorporating films having high dielectric constants are disclosed, in which the high-dielectric constant material is deposited on a semiconductor surface that has been treated to prevent the formation of interfacial oxide between the semiconductor substrate and the high dielectric constant material. The methods of this invention involve implantation of nitrogen ions through the sacrificial oxide layer, thereby forming a nitrided silicon substrate underneath the sacrificial oxide. The sacrificial oxide can then removed, and thereafter layers of high dielectric constant materials can be deposited on the nitrided silicon substrate without the formation of interfacial oxide. Manufacturing devices using the methods of this invention can result in the formation of an overall insulating film having a dielectric constant that more closely reflects the dielectric constant of the high-dielectric constant material.

Abstract: This invention provides methods for reducing the mechanical stresses within dielectric layers filling the gaps in shallow trench isolation (STI) regions on semiconductor wafers. The methods include the sequential deposition of alternating layers of dielectric materials having tensile stress and compressive stress, respectively. The invention also provides methods for adjusting the residual stress in a dielectric film by controlling the relative thicknesses of the alternating layers of dielectric material to provide bilayers having minimal overall stress. Additionally, the invention provides semiconductor devices having the reduced stress dielectric materials within the shallow isolation trenches of the semiconductor wafer. The reduction in stress within and between trenches decreases defects in the shallow isolation materials and thereby decreases source-drain and trench—trench short circuiting.