Patents by Inventor Hyeong-Ju NA
Hyeong-Ju NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12197764Abstract: A memory system is provided to include a memory device and a memory controller. The memory controller is configured to set, for a first memory die, a state check memory block that is used to check a state of data stored in memory blocks included in the first memory die, and the memory controller is further configured to manage, for each of a plurality of temperature periods that are predetermined, (1) a state check page corresponding to a temperature period and included in the state check memory block and (2) a program memory block list indicating information on certain memory blocks programmed at a time that a temperature of the memory system falls within the temperature period.Type: GrantFiled: August 2, 2021Date of Patent: January 14, 2025Assignee: SK HYNIX INC.Inventors: Hyeong Ju Na, Seong Bae Jeon
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Publication number: 20240393949Abstract: In an embodiment of the disclosed technology, a host device may control an operation of writing data to a plurality of types of memory cells included in a memory, through booster logic units respectively corresponding to the plurality of types of memory cells, and a timing thereof. It is possible to prevent performance of a device from degrading due to differences in characteristics of operations in which data are written to the plurality of types of memory cells, and improve performance and efficiency of an operation of writing data to a plurality of memory cells.Type: ApplicationFiled: October 24, 2023Publication date: November 28, 2024Inventor: Hyeong Ju NA
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Publication number: 20240385763Abstract: A storage device may execute an operation of migrating valid data stored in one or more source data sections of a plurality of data sections to one or more destination data sections of the plurality of data sections in response to a request from an external device. When the valid data is migrated from the source data sections to the destination data sections, the storage device may execute an operation of writing meta data for the migrated valid data.Type: ApplicationFiled: October 5, 2023Publication date: November 21, 2024Inventors: Young Ho AHN, Jae Youn JANG, Jin Woo KIM, Hyeong Ju NA, Yoon Won LEE, Jhu Yeong JHIN
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Publication number: 20240377975Abstract: In an embodiment of the disclosed technology, a controller of a host device may manage data stored in a storage device, on the basis of a section which corresponds to a super block of the storage device and includes at least two segments. It is possible to provide measures enabling limited overwrite of a full section including a valid segment and allowing allocation and garbage collection to be performed by the unit of segment, thereby efficiently using a storage space while maintaining a log structure file system of the storage device.Type: ApplicationFiled: October 17, 2023Publication date: November 14, 2024Inventor: Hyeong Ju NA
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Publication number: 20240143211Abstract: In an embodiment of the disclosed technology, since a host device manages data stored in a storage device on the basis of a zone corresponding to a storage block of the storage device, the load of the storage device may be reduced, and the operation efficiency of the storage device may be increased by the control of the host device. Therefore, it is possible to improve the performance of a computing system including the host device and the storage device.Type: ApplicationFiled: October 25, 2023Publication date: May 2, 2024Inventors: Hyeong Ju NA, Jin Woo KIM, Young Ho AHN, Yoon Won LEE
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Patent number: 11630726Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may completely scan each of one or more target memory blocks among the plurality of memory blocks, once in each scan period to detect an error in data stored in the corresponding target memory block and may block an attempted second scan of each target memory block in a scan period in which the corresponding target memory block has already been scanned until the scan period is completed.Type: GrantFiled: March 10, 2021Date of Patent: April 18, 2023Assignee: SK hynix Inc.Inventors: Tae Ha Kim, Jee Yul Kim, Hyeong Ju Na, Kwan Su Lee
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Patent number: 11625324Abstract: A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.Type: GrantFiled: April 16, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Patent number: 11626175Abstract: Various embodiments of the present disclosure generally relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check first information indicating an execution state of a reference operation on each of the memory blocks during a preset target time period, may determine, based on the first information, at least one target memory block, among the plurality of memory blocks, as a target of a refresh operation of rewriting data stored in the target memory block and may execute a refresh operation on the target memory block.Type: GrantFiled: May 17, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Patent number: 11604596Abstract: A storage device may include: a memory device including a plurality of memory blocks; a buffer memory device to store event information; and a memory controller configured to: upon occurrence of the predetermined event while a write operation, store, in the buffer memory device, the event information for the event page, and control the memory device to perform a test read operation to read at least one page in the plurality of memory blocks except the event page, based on the event information; upon failure of the test read operation, control the memory device to perform a migration operation of moving, to a replacement block, data stored in valid pages except a page on which the test read operation has fails among pages included in a memory block on which the test read operation fails.Type: GrantFiled: May 24, 2021Date of Patent: March 14, 2023Assignee: SK hynix Inc.Inventors: Tae Ha Kim, Jee Yul Kim, Hyeong Ju Na
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Patent number: 11513738Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to embodiments of the present disclosure, a memory system may determine whether the memory system is in a read-intensive state; when determined that the memory system is in the read-intensive state, process a write request received from a host using at least one first type memory block among the plurality of memory blocks, and migrate data stored in a second type memory block to the at least one first type memory block; and set a number of bits that can be stored in a memory cell included in the first type memory block to be less than a number of bits that can be stored in a memory cell included in the second type memory block.Type: GrantFiled: May 19, 2021Date of Patent: November 29, 2022Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Publication number: 20220300187Abstract: A memory system is provided to include a memory device and a memory controller. The memory controller is configured to set, for a first memory die, a state check memory block that is used to check a state of data stored in memory blocks included in the first memory die, and the memory controller is further configured to manage, for each of a plurality of temperature periods that are predetermined, (1) a state check page corresponding to a temperature period and included in the state check memory block and (2) a program memory block list indicating information on certain memory blocks programmed at a time that a temperature of the memory system falls within the temperature period.Type: ApplicationFiled: August 2, 2021Publication date: September 22, 2022Inventors: Hyeong Ju NA, Seong Bae JEON
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Patent number: 11436140Abstract: A memory system may include a memory device including a plurality of memory blocks and a controller suitable for determining whether to change from a normal mode to a dirty mode based on a size of free space of a host a sum of an amount of restoration of garbage collection for victim blocks and a size of all free blocks in the memory device. In the dirty mode, the controller controls the memory device to perform a garbage collection operation on the victim blocks at a frequency greater than frequency at which a garbage collection operation is performed in the normal mode.Type: GrantFiled: August 24, 2020Date of Patent: September 6, 2022Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Publication number: 20220229594Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to embodiments of the present disclosure, a memory system may determine whether the memory system is in a read-intensive state; when determined that the memory system is in the read-intensive state, process a write request received from a host using at least one first type memory block among the plurality of memory blocks, and migrate data stored in a second type memory block to the at least one first type memory block; and set a number of bits that can be stored in a memory cell included in the first type memory block to be less than a number of bits that can be stored in a memory cell included in the second type memory block.Type: ApplicationFiled: May 19, 2021Publication date: July 21, 2022Inventor: Hyeong Ju NA
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Publication number: 20220223217Abstract: Various embodiments of the present disclosure generally relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check first information indicating an execution state of a reference operation on each of the memory blocks during a preset target time period, may determine, based on the first information, at least one target memory block, among the plurality of memory blocks, as a target of a refresh operation of rewriting data stored in the target memory block and may execute a refresh operation on the target memory block.Type: ApplicationFiled: May 17, 2021Publication date: July 14, 2022Inventor: Hyeong Ju NA
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Patent number: 11379363Abstract: A controller, a memory system, and operating methods thereof are disclosed. A memory system includes at least one nonvolatile memory device and a controller configured to control the nonvolatile memory device. The at least one nonvolatile memory device includes a super block including a plurality of way interleaving memory blocks and each of memory cells included in the plurality of way interleaving memory blocks operates in a first mode which stores N-bit (wherein N is a natural number of 2 or more) data. The controller generates a reproduction super block by replacing at least one bad block among the plurality of way interleaving memory blocks included in the super block with a non-way interleaving spare block and sets each of memory cells included in the non-way interleaving spare block to operate in a second mode which stores M-bit (wherein M is a natural number smaller than N) data.Type: GrantFiled: March 18, 2020Date of Patent: July 5, 2022Assignee: SK hynix Inc.Inventors: Jeen Park, Hyeong Ju Na
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Publication number: 20220147261Abstract: A storage device may include: a memory device including a plurality of memory blocks; a buffer memory device to store event information; and a memory controller configured to: upon occurrence of the predetermined event while a write operation, store, in the buffer memory device, the event information for the event page, and control the memory device to perform a test read operation to read at least one page in the plurality of memory blocks except the event page, based on the event information; upon failure of the test read operation, control the memory device to perform a migration operation of moving, to a replacement block, data stored in valid pages except a page on which the test read operation has fails among pages included in a memory block on which the test read operation fails.Type: ApplicationFiled: May 24, 2021Publication date: May 12, 2022Inventors: Tae Ha KIM, Jee Yul KIM, Hyeong Ju NA
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Publication number: 20220114089Abstract: A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.Type: ApplicationFiled: April 16, 2021Publication date: April 14, 2022Inventor: Hyeong Ju NA
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Publication number: 20220091932Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may completely scan each of one or more target memory blocks among the plurality of memory blocks, once in each scan period to detect an error in data stored in the corresponding target memory block and may block an attempted second scan of each target memory block in a scan period in which the corresponding target memory block has already been scanned until the scan period is completed.Type: ApplicationFiled: March 10, 2021Publication date: March 24, 2022Inventors: Tae Ha KIM, Jee Yul KIM, Hyeong Ju NA, Kwan Su LEE
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Patent number: 11157401Abstract: A data storage device may include a nonvolatile memory device including a plurality of memory blocks and a controller configured to perform a block scan operation for checking valid page counts of closed blocks, when the number of free blocks among the plurality of memory blocks is equal to or less than a threshold number, select a victim block from the closed blocks among the plurality of memory blocks, and perform a garbage collection operation on the victim block. The controller may change an index of a scan start block among the closed blocks whenever performing the block scan operation.Type: GrantFiled: November 1, 2019Date of Patent: October 26, 2021Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Patent number: 11099981Abstract: An operating method of a memory system includes determining whether a write command currently provided is a sequential write command or a random write command, performing a garbage collection operation based on whether a total capacity of data provided after a preceding garbage collection operation exceeds a sequential command threshold value, when it is determined that the write command is a sequential write command, and performing the garbage collection operation based on whether a number of sequential write commands among a set number of commands currently provided, is greater than or equal to a predetermined number and whether the total capacity of the data provided after the preceding garbage collection operation exceeds the sequential command threshold value, when it is determined that the write command is a random write command.Type: GrantFiled: December 5, 2018Date of Patent: August 24, 2021Assignee: SK hynix Inc.Inventors: Jong-Min Lee, Hyeong-Ju Na