Patents by Inventor Hyeong-Ju NA

Hyeong-Ju NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210240613
    Abstract: A memory system may include a memory device including a plurality of memory blocks and a controller suitable for determining whether to change from a normal mode to a dirty mode based on a size of free space of a host a sum of an amount of restoration of garbage collection for victim blocks and a size of all free blocks in the memory device. In the dirty mode, the controller controls the memory device to perform a garbage collection operation on the victim blocks at a frequency greater than frequency at which a garbage collection operation is performed in the normal mode.
    Type: Application
    Filed: August 24, 2020
    Publication date: August 5, 2021
    Inventor: Hyeong Ju Na
  • Patent number: 10929289
    Abstract: Various embodiments relate to a controller, a memory system and an operating method thereof. In one embodiment, a memory system may include a nonvolatile memory device including a plurality of super blocks each comprising a plurality of memory blocks; and a controller configured to control the nonvolatile memory device, wherein the controller is configured to: determine, based on a number of low performance super blocks among the plurality of super blocks, a dirty status threshold value for determining a dirty status of the nonvolatile memory device; determine whether the nonvolatile memory device is in the dirty status based on a number of free super blocks among the plurality of super blocks and the dirty status threshold value; and perform a garbage collection operation on the plurality of super blocks when it is determined that the nonvolatile memory device is in the dirty status.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeong Ju Na, Jeen Park
  • Publication number: 20210026767
    Abstract: A controller, a memory system, and operating methods thereof are disclosed. A memory system includes at least one nonvolatile memory device and a controller configured to control the nonvolatile memory device. The at least one nonvolatile memory device includes a super block including a plurality of way interleaving memory blocks and each of memory cells included in the plurality of way interleaving memory blocks operates in a first mode which stores N-bit (wherein N is a natural number of 2 or more) data. The controller generates a reproduction super block by replacing at least one bad block among the plurality of way interleaving memory blocks included in the super block with a non-way interleaving spare block and sets each of memory cells included in the non-way interleaving spare block to operate in a second mode which stores M-bit (wherein M is a natural number smaller than N) data.
    Type: Application
    Filed: March 18, 2020
    Publication date: January 28, 2021
    Inventors: Jeen PARK, Hyeong Ju NA
  • Publication number: 20200394134
    Abstract: A data storage device may include a nonvolatile memory device including a plurality of memory blocks and a controller configured to perform a block scan operation for checking valid page counts of closed blocks, when the number of free blocks among the plurality of memory blocks is equal to or less than a threshold number, select a victim block from the closed blocks among the plurality of memory blocks, and perform a garbage collection operation on the victim block. The controller may change an index of a scan start block among the closed blocks whenever performing the block scan operation.
    Type: Application
    Filed: November 1, 2019
    Publication date: December 17, 2020
    Inventor: Hyeong Ju NA
  • Publication number: 20200310967
    Abstract: Various embodiments relate to a controller, a memory system and an operating method thereof. In one embodiment, a memory system may include a nonvolatile memory device including a plurality of super blocks each comprising a plurality of memory blocks; and a controller configured to control the nonvolatile memory device, wherein the controller is configured to: determine, based on a number of low performance super blocks among the plurality of super blocks, a dirty status threshold value for determining a dirty status of the nonvolatile memory device; determine whether the nonvolatile memory device is in the dirty status based on a number of free super blocks among the plurality of super blocks and the dirty status threshold value; and perform a garbage collection operation on the plurality of super blocks when it is determined that the nonvolatile memory device is in the dirty status.
    Type: Application
    Filed: October 10, 2019
    Publication date: October 1, 2020
    Inventors: Hyeong Ju NA, Jeen PARK
  • Patent number: 10789164
    Abstract: A memory system includes: a memory device including a closed memory block; an update block detector detecting a total sum of valid page decrease amounts and the number of update blocks based on the number of valid pages of the closed memory block that are counted before and after a map update operation; and a garbage collector performing a garbage collection operation on a victim block, based on the number of free blocks in the memory device, the counted number of the update blocks and the calculated total sum of the valid page decrease amounts.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeong-Ju Na, Jong-Min Lee
  • Patent number: 10783074
    Abstract: A controller includes a memory device storing data and including a memory interface a processor; and a memory, wherein, when data is stored in all pages of an open block of a memory device, the processor determines a number of valid pages in the open block and performs a garbage collection on the open block when the number of valid page(s) is determined to be less than or equal to a threshold value, wherein the number ranges from zero to the total number of pages in the open block.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyeong-Ju Na
  • Patent number: 10747664
    Abstract: A memory system includes: a memory device; a candidate logical block address (LBA) sensor suitable for detecting a start LBA of a sequential workload as a candidate LBA, and, when a ratio of the number of update blocks to a total sum of valid page decrease amounts is less than a first threshold value, caching the candidate LBA in a loop cache; and a garbage collector suitable for performing a garbage collection operation on a victim block, when the number of free blocks in the memory device is less than a second threshold value and greater than or equal to a third threshold value and a start LBA of a subsequent sequential workload is not the same as the cached candidate LBA.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeong-Ju Na, Jong-Min Lee
  • Patent number: 10740229
    Abstract: A memory system including: a memory device having an open block and a closed memory block; a page counting unit counting the number of program pages in the open block whenever a data is programmed in the open block, and counting the number of valid pages of the closed memory block; a valid page decrease amount counting unit calculating a total sum of valid pages decreased in the closed memory block before and after a map update operation; and a garbage collecting unit performing a garbage collection operation onto a victim block when the number of free blocks included in the memory device is less than a first threshold value and greater than a second threshold value, and a ratio of the number of the program pages in the open block to the total sum of the valid pages decreased is greater than or equal to a fourth threshold value.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeong-Ju Na, Jong-Min Lee
  • Patent number: 10678687
    Abstract: A memory system includes: a memory device; a valid page counter for counting the number of valid pages of each closed block in the memory device before and after a map update operation; a maximum valid page decrease amount detector for detecting a maximum valid page decrease amount by calculating a valid page decrease amount for each closed memory block based on the number of the valid pages for the corresponding closed memory block, so as to calculate a total sum of valid page decrease amounts; and a garbage collector for performing a garbage collection operation on a victim block in the memory device, when the number of free blocks in the memory device is less than a first threshold value and greater than a second threshold value and a ratio of the maximal valid page decrease amount to the total sum of the valid page decrease amounts is a third threshold value or less.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeong-Ju Na, Jong-Min Lee
  • Publication number: 20200019497
    Abstract: A memory system includes: a memory device; a candidate logical block address (LBA) sensor suitable for detecting a start LBA of a sequential workload as a candidate LBA, and, when a ratio of the number of update blocks to a total sum of valid page decrease amounts is less than a first threshold value, caching the candidate LBA in a loop cache; and a garbage collector suitable for performing a garbage collection operation on a victim block, when the number of free blocks in the memory device is less than a second threshold value and greater than or equal to a third threshold value and a start LBA of a subsequent sequential workload is not the same as the cached candidate LBA.
    Type: Application
    Filed: December 31, 2018
    Publication date: January 16, 2020
    Inventors: Hyeong-Ju NA, Jong-Min LEE
  • Publication number: 20200019496
    Abstract: A memory system includes: a memory device; a valid page counter for counting the number of valid pages of each closed block in the memory device before and after a map update operation; a maximum valid page decrease amount detector for detecting a maximum valid page decrease amount by calculating a valid page decrease amount for each closed memory block based on the number of the valid pages for the corresponding closed memory block, so as to calculate a total sum of valid page decrease amounts; and a garbage collector for performing a garbage collection operation on a victim block in the memory device, when the number of free blocks in the memory device is less than a first threshold value and greater than a second threshold value and a ratio of the maximal valid page decrease amount to the total sum of the valid page decrease amounts is a third threshold value or less.
    Type: Application
    Filed: December 31, 2018
    Publication date: January 16, 2020
    Inventors: Hyeong-Ju NA, Jong-Min LEE
  • Publication number: 20200019495
    Abstract: A memory system includes: a memory device including a closed memory block; an update block detector detecting a total sum of valid page decrease amounts and the number of update blocks based on the number of valid pages of the closed memory block that are counted before and after a map update operation; and a garbage collector performing a garbage collection operation on a victim block, based on the number of free blocks in the memory device, the counted number of the update blocks and the calculated total sum of the valid page decrease amounts.
    Type: Application
    Filed: December 19, 2018
    Publication date: January 16, 2020
    Inventors: Hyeong-Ju NA, Jong-Min LEE
  • Publication number: 20200012597
    Abstract: A memory system including: a memory device having an open block and a closed memory block; a page counting unit counting the number of program pages in the open block whenever a data is programmed in the open block, and counting the number of valid pages of the closed memory block; a valid page decrease amount counting unit calculating a total sum of valid pages decreased in the closed memory block before and after a map update operation; and a garbage collecting unit performing a garbage collection operation onto a victim block when the number of free blocks included in the memory device is less than a first threshold value and greater than a second threshold value, and a ratio of the number of the program pages in the open block to the total sum of the valid pages decreased is greater than or equal to a fourth threshold value.
    Type: Application
    Filed: December 20, 2018
    Publication date: January 9, 2020
    Inventors: Hyeong-Ju NA, Jong-Min LEE
  • Publication number: 20190347197
    Abstract: An operating method of a memory system includes determining whether a write command currently provided is a sequential write command or a random write command, performing a garbage collection operation based on whether a total capacity of data provided after a preceding garbage collection operation exceeds a sequential command threshold value, when it is determined that the write command is a sequential write command, and performing the garbage collection operation based on whether a number of sequential write commands among a set number of commands currently provided, is greater than or equal to a predetermined number and whether the total capacity of the data provided after the preceding garbage collection operation exceeds the sequential command threshold value, when it is determined that the write command is a random write command.
    Type: Application
    Filed: December 5, 2018
    Publication date: November 14, 2019
    Inventors: Jong-Min LEE, Hyeong-Ju NA
  • Publication number: 20190266082
    Abstract: A controller includes a memory device storing data and including a memory interface a processor; and a memory, wherein, when data is stored in all pages of an open block of a memory device, the processor determines a number of valid pages in the open block and performs a garbage collection on the open block when the number of valid page(s) is determined to be less than or equal to a threshold value, wherein the number ranges from zero to the total number of pages in the open block.
    Type: Application
    Filed: October 24, 2018
    Publication date: August 29, 2019
    Inventor: Hyeong-Ju NA