Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

Abstract: A method of fabricating a semiconductor package may include forming a plating layer on a surface of a substrate body. A circuit resist pattern and a monitoring resist pattern may be formed on the plating layer, and the plating layer may be etched using the circuit resist pattern and the monitoring resist pattern as etch masks, thereby forming circuit patterns and sub-patterns of a monitoring pattern. A residual rate of the circuit patterns may be monitored by inspecting the number of the sub-patterns of the monitoring pattern remaining on the substrate body after an etch process for forming the circuit patterns and the sub-patterns of the monitoring pattern. A semiconductor chip may be bonded to the circuit patterns using inner connectors.

Abstract: A method of fabricating a semiconductor package may include forming a plating layer on a surface of a substrate body. A circuit resist pattern and a monitoring resist pattern may be formed on the plating layer, and the plating layer may be etched using the circuit resist pattern and the monitoring resist pattern as etch masks, thereby forming circuit patterns and sub-patterns of a monitoring pattern. A residual rate of the circuit patterns may be monitored by inspecting the number of the sub-patterns of the monitoring pattern remaining on the substrate body after an etch process for forming the circuit patterns and the sub-patterns of the monitoring pattern. A semiconductor chip may be bonded to the circuit patterns using inner connectors.

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

Abstract: Wafer level packages are provided. The wafer level package includes alignment marks disposed at a first surface of a protection wafer, a semiconductor die disposed on the first surface of the protection wafer to be spaced apart from the alignment marks, a first photosensitive dielectric layer covering the semiconductor die and having a flat top surface, and a second dielectric layer covering the flat top surface of the first photosensitive dielectric layer. Redistribution lines are disposed between the first photosensitive dielectric layer and the second dielectric layer and electrically connected to the semiconductor die through first opening portions penetrating the first photosensitive dielectric layer. Outer connectors are disposed on the second dielectric layer and electrically connected to the redistribution lines through second opening portions penetrating the second dielectric layer.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

Abstract: A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided.

Abstract: A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.