Patents by Inventor Hyeong-Soo JEONG
Hyeong-Soo JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817175Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.Type: GrantFiled: May 2, 2022Date of Patent: November 14, 2023Assignee: SK hynix Inc.Inventors: Mino Kim, Hyeong Soo Jeong
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Patent number: 11670393Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.Type: GrantFiled: November 12, 2021Date of Patent: June 6, 2023Assignee: SK hynix Inc.Inventors: Dong Beom Lee, Eun Je Kim, Hyeong Soo Jeong
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Patent number: 11636910Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.Type: GrantFiled: May 3, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Hyeong Soo Jeong, Dong Beom Lee
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Patent number: 11636909Abstract: A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.Type: GrantFiled: May 6, 2021Date of Patent: April 25, 2023Assignee: SK hynix Inc.Inventors: Hyun Seung Kim, Hyeong Soo Jeong
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Patent number: 11626186Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.Type: GrantFiled: April 30, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventors: Dong Beom Lee, Hyeong Soo Jeong
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Publication number: 20230076494Abstract: An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.Type: ApplicationFiled: November 29, 2021Publication date: March 9, 2023Applicant: SK hynix Inc.Inventors: Dong Beom LEE, Hyeong Soo JEONG
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Publication number: 20230041988Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.Type: ApplicationFiled: November 12, 2021Publication date: February 9, 2023Applicant: SK hynix Inc.Inventors: Dong Beom LEE, Eun Je KIM, Hyeong Soo JEONG
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Publication number: 20220283917Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.Type: ApplicationFiled: April 30, 2021Publication date: September 8, 2022Applicant: SK hynix Inc.Inventors: Dong Beom LEE, Hyeong Soo JEONG
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Publication number: 20220262416Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Applicant: SK hynix Inc.Inventors: Mino KIM, Hyeong Soo JEONG
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Publication number: 20220262448Abstract: A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.Type: ApplicationFiled: May 6, 2021Publication date: August 18, 2022Applicant: SK hynix Inc.Inventors: Hyun Seung KIM, Hyeong Soo JEONG
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Publication number: 20220254427Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.Type: ApplicationFiled: May 3, 2021Publication date: August 11, 2022Applicant: SK hynix Inc.Inventors: Hyeong Soo JEONG, Dong Beom LEE
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Patent number: 11348625Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.Type: GrantFiled: February 26, 2021Date of Patent: May 31, 2022Assignee: SK hynix Inc.Inventors: Mino Kim, Hyeong Soo Jeong
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Publication number: 20210183424Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Applicant: SK hynix Inc.Inventors: Mino KIM, Hyeong Soo JEONG
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Patent number: 11003530Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. Wherein, the storage circuit stores the fuse data and outputs it as a storage signal and the parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal, the fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal, the error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.Type: GrantFiled: September 30, 2019Date of Patent: May 11, 2021Assignee: SK hynix Inc.Inventors: Hyeong Soo Jeong, Gang Sik Lee
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Patent number: 10943629Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.Type: GrantFiled: December 30, 2019Date of Patent: March 9, 2021Assignee: SK hynix Inc.Inventors: Seung Hun Lee, Hyeong Soo Jeong
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Publication number: 20200388311Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.Type: ApplicationFiled: December 30, 2019Publication date: December 10, 2020Applicant: SK hynix Inc.Inventors: Seung Hun LEE, Hyeong Soo JEONG
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Publication number: 20200192755Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. The storage circuit stores the fuse data and outputs it as a storage signal. The parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal. The fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal. The error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.Type: ApplicationFiled: September 30, 2019Publication date: June 18, 2020Applicant: SK hynix Inc.Inventors: Hyeong Soo JEONG, Gang Sik LEE
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Patent number: 10416705Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.Type: GrantFiled: July 6, 2017Date of Patent: September 17, 2019Assignee: SK hynix Inc.Inventors: Geun Ho Choi, Hyeong Soo Jeong
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Patent number: 10366773Abstract: An electrical fuse (E-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the E-fuse circuit. The E-fuse circuit comprising: a boot-up controller configured to generate at least one fuse address and a sensing enable signal, an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and configured to output fuse data including failed data if a failure has occurred in an E-fuse of the plurality of fuse sets, based on the fuse address and the sensing enable signal, a fail controller configured to detect failed data from the fuse data, and output a failed signal and a failed address storage circuit configured to store a failed address from among the fuse addresses based on the failed signal.Type: GrantFiled: June 15, 2017Date of Patent: July 30, 2019Assignee: SK hynix Inc.Inventor: Hyeong Soo Jeong
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Patent number: 10170197Abstract: A semiconductor device includes: first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.Type: GrantFiled: June 20, 2017Date of Patent: January 1, 2019Assignee: SK Hynix Inc.Inventors: Hyeong-Soo Jeong, Jong-Ho Son