Patents by Inventor Hyeong-Soo JEONG

Hyeong-Soo JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220283917
    Abstract: An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.
    Type: Application
    Filed: April 30, 2021
    Publication date: September 8, 2022
    Applicant: SK hynix Inc.
    Inventors: Dong Beom LEE, Hyeong Soo JEONG
  • Publication number: 20220262416
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Applicant: SK hynix Inc.
    Inventors: Mino KIM, Hyeong Soo JEONG
  • Publication number: 20220262448
    Abstract: A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 18, 2022
    Applicant: SK hynix Inc.
    Inventors: Hyun Seung KIM, Hyeong Soo JEONG
  • Publication number: 20220254427
    Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 11, 2022
    Applicant: SK hynix Inc.
    Inventors: Hyeong Soo JEONG, Dong Beom LEE
  • Patent number: 11348625
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventors: Mino Kim, Hyeong Soo Jeong
  • Publication number: 20210183424
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Applicant: SK hynix Inc.
    Inventors: Mino KIM, Hyeong Soo JEONG
  • Patent number: 11003530
    Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. Wherein, the storage circuit stores the fuse data and outputs it as a storage signal and the parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal, the fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal, the error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeong Soo Jeong, Gang Sik Lee
  • Patent number: 10943629
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Hyeong Soo Jeong
  • Publication number: 20200388311
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.
    Type: Application
    Filed: December 30, 2019
    Publication date: December 10, 2020
    Applicant: SK hynix Inc.
    Inventors: Seung Hun LEE, Hyeong Soo JEONG
  • Publication number: 20200192755
    Abstract: A semiconductor apparatus includes a fuse array, storage circuit, parity circuit, fuse data register, parity data register, and error correction circuit. The fuse array stores information about fail addresses and outputs the stored information as fuse data during a boot-up operation. The storage circuit stores the fuse data and outputs it as a storage signal. The parity circuit performs a parity operation based on the storage signal and outputs a result of the parity operation as a parity signal. The fuse data register receives and stores the fuse data and outputs the stored data as a fuse register output signal. The parity data register receives and stores the parity signal and outputs the stored information as a parity register output signal. The error correction circuit corrects an error of the fuse register output signal based on the parity register output signal and outputs the error-corrected signal as repair information.
    Type: Application
    Filed: September 30, 2019
    Publication date: June 18, 2020
    Applicant: SK hynix Inc.
    Inventors: Hyeong Soo JEONG, Gang Sik LEE
  • Patent number: 10416705
    Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Hyeong Soo Jeong
  • Patent number: 10366773
    Abstract: An electrical fuse (E-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the E-fuse circuit. The E-fuse circuit comprising: a boot-up controller configured to generate at least one fuse address and a sensing enable signal, an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and configured to output fuse data including failed data if a failure has occurred in an E-fuse of the plurality of fuse sets, based on the fuse address and the sensing enable signal, a fail controller configured to detect failed data from the fuse data, and output a failed signal and a failed address storage circuit configured to store a failed address from among the fuse addresses based on the failed signal.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyeong Soo Jeong
  • Patent number: 10170197
    Abstract: A semiconductor device includes: first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventors: Hyeong-Soo Jeong, Jong-Ho Son
  • Patent number: 10102918
    Abstract: A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 16, 2018
    Assignee: SK hynix Inc.
    Inventors: Hyeong Soo Jeong, Tae Kyun Shin, Young Bo Shim
  • Publication number: 20180197621
    Abstract: An electrical fuse (E-fuse) circuit is disclosed, which relates to a technology for processing a failed part of the E-fuse circuit. The E-fuse circuit may be configured to detect failed data and or store a failed address.
    Type: Application
    Filed: June 15, 2017
    Publication date: July 12, 2018
    Applicant: SK hynix Inc.
    Inventor: Hyeong Soo JEONG
  • Publication number: 20180166144
    Abstract: A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third internal command based on a command/address signal. The semiconductor device also includes a driving signal generation circuit suitable for enabling a fuse driving signal for reading fuse data from a nonvolatile memory circuit, where the fuse signal is enabled while the second internal command is inputted a predetermined number of times. Further included is an output circuit suitable for outputting the fuse data in response to the third internal command.
    Type: Application
    Filed: July 21, 2017
    Publication date: June 14, 2018
    Applicant: SK hynix Inc.
    Inventors: Hyeong Soo JEONG, Tae Kyun SHIN, Young Bo SHIM
  • Publication number: 20180150100
    Abstract: A training device may include a pattern generation circuit configured to generate a pattern signal in response to a read command, a delay calculation circuit configured to calculate a delay amount based on comparison results between a generation timing of the pattern signal and generation timings of pattern signals which are generated from one or more other training devices and transmitted to a corresponding training device, and a delay adjusting circuit configured to adjust a delay of a DQ signal in a chip including the corresponding training device, based on the delay amount.
    Type: Application
    Filed: July 6, 2017
    Publication date: May 31, 2018
    Applicant: SK hynix Inc.
    Inventors: Geun Ho CHOI, Hyeong Soo JEONG
  • Publication number: 20180096731
    Abstract: A semiconductor device includes: first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.
    Type: Application
    Filed: June 20, 2017
    Publication date: April 5, 2018
    Inventors: Hyeong-Soo JEONG, Jong-Ho SON