Patents by Inventor Hyeong-Sun Hong
Hyeong-Sun Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11482285Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: GrantFiled: July 23, 2020Date of Patent: October 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-woo Kim, Jae-Kyu Lee, Ki-seok Suh, Hyeong-sun Hong, Yoo-sang Hwang, Gwan-hyeob Koh
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Patent number: 11251307Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.Type: GrantFiled: September 4, 2018Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-jin Park, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
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Publication number: 20200357466Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-woo KIM, Jae-Kyu LEE, Ki-seok SUH, Hyeong-sun HONG, Yoo-sang HWANG, Gwan-hyeob KOH
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Patent number: 10777276Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: GrantFiled: August 6, 2019Date of Patent: September 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-woo Kim, Jae-kyu Lee, Ki-seok Suh, Hyeong-sun Hong, Yoo-sang Hwang, Gwan-hyeob Koh
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Publication number: 20190362791Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-woo KIM, Jae-kyu LEE, Ki-seok SUH, Hyeong-sun HONG, Yoo-sang HWANG, Gwan-hyeob KOH
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Patent number: 10468103Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: GrantFiled: November 29, 2017Date of Patent: November 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-woo Kim, Jae-kyu Lee, Ki-seok Suh, Hyeong-sun Hong, Yoo-sang Hwang, Gwan-hyeob Koh
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Publication number: 20190074380Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.Type: ApplicationFiled: September 4, 2018Publication date: March 7, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-jin PARK, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
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Publication number: 20190074381Abstract: A device including a two-dimensional (2D) material includes a substrate including a recess recessed from a main surface of the substrate and extending in a first direction, a 2D material pattern on the substrate and intersecting with the recess of the substrate, a gate structure contacting the 2D material pattern and extending in the first direction along the recess of the substrate, a first electrode contacting a first end of the 2D material pattern, and a second electrode contacting a second end of the 2D material pattern. The 2D material pattern extends in a second direction and includes atomic layers that are parallel to a surface of the substrate.Type: ApplicationFiled: September 4, 2018Publication date: March 7, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Tae-jin Park, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
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Publication number: 20180158526Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.Type: ApplicationFiled: November 29, 2017Publication date: June 7, 2018Inventors: Sung-woo KIM, Jae-kyu LEE, Ki-seok SUH, Hyeong-sun HONG, Yoo-sang HWANG, Gwan-hyeob KOH
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Patent number: 9536868Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: GrantFiled: October 5, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
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Patent number: 9299827Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: GrantFiled: October 16, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Soo-Ho Shin, Ho-In Ryu, Hyeong-Sun Hong
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Patent number: 9276074Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.Type: GrantFiled: February 7, 2013Date of Patent: March 1, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jay-Bok Choi, Yoo-Sang Hwang, Ah-Young Kim, Ye-Ro Lee, Gyo-Young Jin, Hyeong-sun Hong
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Publication number: 20160035714Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: ApplicationFiled: October 5, 2015Publication date: February 4, 2016Inventors: KEUN-NAM KIM, SUN-YOUNG PARK, SOO-HO SHIN, KYE-HEE YEOM, HYEON-WOO JANG, JIN-WON JEONG, CHANG-HYUN CHO, HYEONG-SUN HONG
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Patent number: 9240415Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.Type: GrantFiled: June 24, 2014Date of Patent: January 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Kyung Park, Ki-Jae Hur, Hyeong-Sun Hong, Se-Young Kim, Jun-Hee Lim
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Patent number: 9177891Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.Type: GrantFiled: October 3, 2013Date of Patent: November 3, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-Nam Kim, Sun-Young Park, Soo-Ho Shin, Kye-Hee Yeom, Hyeon-Woo Jang, Jin-Won Jeong, Chang-Hyun Cho, Hyeong-Sun Hong
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Patent number: 8957474Abstract: A MOS transistor, can include a u-shaped cross-sectional channel region including spaced apart protruding portions separated by a trench and connected to one another by a connecting portion of the channel region at lower ends of the spaced apart protruding portions of the channel region. First and second impurity regions can be located at opposite ends of the -shaped cross-sectional channel region and separated from one another by the trench. A gate electrode can cover at least a planar face of the u-shaped cross-sectional channel region including the spaced apart protruding portions and the connecting portion and exposing the first and second impurity regions.Type: GrantFiled: May 15, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Ik Kim, Ji-Young Kim, Hyeong-Sun Hong
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Publication number: 20150035025Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: ApplicationFiled: October 16, 2014Publication date: February 5, 2015Inventors: Bong-Soo KIM, Soo-Ho SHIN, Ho-In RYU, Hyeong-Sun HONG
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Publication number: 20150008530Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.Type: ApplicationFiled: June 24, 2014Publication date: January 8, 2015Inventors: Won-Kyung Park, Ki-Jae Hur, Hyeong-Sun Hong, Se-Young Kim, Jun-Hee Lim
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Patent number: 8884340Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: GrantFiled: November 17, 2011Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8872262Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.Type: GrantFiled: May 18, 2010Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Soo Kim, Hyeong-Sun Hong, Soo-Ho Shin, Ho-In Ryu